DBG_TRACEEXT 332 src/dps8/doAppendCycleAPUDataRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 288 src/dps8/doAppendCycleAPUDataRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 293 src/dps8/doAppendCycleAPUDataStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 403 src/dps8/doAppendCycleIndirectWordFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 580 src/dps8/doAppendCycleInstructionFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 331 src/dps8/doAppendCycleOperandRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 685 src/dps8/doAppendCycleOperandRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 291 src/dps8/doAppendCycleOperandStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 328 src/dps8/doAppendCycleRTCDOperandFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 1896 src/dps8/dps8_append.c sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); DBG_TRACEEXT 1161 src/dps8/dps8_cpu.c { "TRACEEXT", DBG_TRACEEXT, NULL }, DBG_TRACEEXT 2159 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "set_temporary_absolute_mode bit 29 sets XSF to 0\n"); DBG_TRACEEXT 2696 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fetchCycle bit 29 sets XSF to 0\n"); DBG_TRACEEXT 2799 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 2807 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 420 src/dps8/dps8_decimal.c DBG_TRACEEXT 422 src/dps8/dps8_decimal.c DBG_TRACEEXT 450 src/dps8/dps8_decimal.c DBG_TRACEEXT 465 src/dps8/dps8_decimal.c DBG_TRACEEXT 468 src/dps8/dps8_decimal.c DBG_TRACEEXT 476 src/dps8/dps8_decimal.c DBG_TRACEEXT 482 src/dps8/dps8_decimal.c DBG_TRACEEXT 501 src/dps8/dps8_decimal.c DBG_TRACEEXT 530 src/dps8/dps8_decimal.c DBG_TRACEEXT 547 src/dps8/dps8_decimal.c DBG_TRACEEXT 569 src/dps8/dps8_decimal.c DBG_TRACEEXT 582 src/dps8/dps8_decimal.c DBG_TRACEEXT 600 src/dps8/dps8_decimal.c DBG_TRACEEXT 604 src/dps8/dps8_decimal.c DBG_TRACEEXT 611 src/dps8/dps8_decimal.c DBG_TRACEEXT 620 src/dps8/dps8_decimal.c DBG_TRACEEXT 645 src/dps8/dps8_decimal.c DBG_TRACEEXT 669 src/dps8/dps8_decimal.c DBG_TRACEEXT 687 src/dps8/dps8_decimal.c DBG_TRACEEXT 695 src/dps8/dps8_decimal.c DBG_TRACEEXT 32 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ DBG_TRACEEXT 42 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ DBG_TRACEEXT 562 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteCache addr %06o\n", p->cachedAddr); DBG_TRACEEXT 572 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } DBG_TRACEEXT 600 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } DBG_TRACEEXT 626 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadCache addr %06o\n", address); DBG_TRACEEXT 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } DBG_TRACEEXT 653 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 656 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } DBG_TRACEEXT 673 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 676 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 694 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); DBG_TRACEEXT 697 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", p->address, n); DBG_TRACEEXT 733 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); DBG_TRACEEXT 737 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx %ld addr %06o n %u\n", eisaddr_idx, p->address, n); DBG_TRACEEXT 763 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", cpu.du.Dk_PTR_W[eisaddr_idx]); DBG_TRACEEXT 765 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", p->address); DBG_TRACEEXT 776 src/dps8/dps8_eis.c DBG_TRACEEXT 778 src/dps8/dps8_eis.c DBG_TRACEEXT 798 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); DBG_TRACEEXT 814 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 818 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 822 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 838 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 841 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 860 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); DBG_TRACEEXT 876 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 880 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 884 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 900 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 903 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 965 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, cpu.du.TAk[k - 1], residue, c); DBG_TRACEEXT 967 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, e -> TA [k - 1], residue, c); DBG_TRACEEXT 1280 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); DBG_TRACEEXT 1285 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARb %u\n", k - 1); DBG_TRACEEXT 1312 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARa %u\n", k - 1); DBG_TRACEEXT 1428 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); DBG_TRACEEXT 1435 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "initial CN%u %u\n", k, CN); DBG_TRACEEXT 1470 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %o\n", k, e->N[k-1]); DBG_TRACEEXT 1514 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA4\n", DBG_TRACEEXT 1538 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA6\n", DBG_TRACEEXT 1552 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 1564 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA9\n", DBG_TRACEEXT 1719 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): N%u %0o\n", k, e->N[k-1]); DBG_TRACEEXT 1817 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", cpu.du.Dk_PTR_W[k-1], a->cPos, a->bPos, k, e->N[k-1]); DBG_TRACEEXT 1819 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", a->address, a->cPos, a->bPos, k, e->N[k-1]); DBG_TRACEEXT 1857 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d AR%d\n", k, n); DBG_TRACEEXT 1877 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]); DBG_TRACEEXT 1884 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d opdesc %012"PRIo64"\n", k, opDesc); DBG_TRACEEXT 1885 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %u\n", k, e->N[k-1]); DBG_TRACEEXT 2108 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); DBG_TRACEEXT 2113 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); DBG_TRACEEXT 2116 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o\n", augend); DBG_TRACEEXT 2122 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd force augend 0%o\n", augend); DBG_TRACEEXT 2141 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); DBG_TRACEEXT 2250 src/dps8/dps8_eis.c DBG_TRACEEXT 2281 src/dps8/dps8_eis.c DBG_TRACEEXT 2332 src/dps8/dps8_eis.c DBG_TRACEEXT 2370 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, DBG_TRACEEXT 2376 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); DBG_TRACEEXT 2382 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o\n", augend); DBG_TRACEEXT 2387 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); DBG_TRACEEXT 2445 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); DBG_TRACEEXT 2450 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); DBG_TRACEEXT 2456 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o\n", minued); DBG_TRACEEXT 2461 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o subtractend 0%o difference 0%o\n", minued, subtractend, difference); DBG_TRACEEXT 2482 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd r 0%o\n", r); DBG_TRACEEXT 2484 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); DBG_TRACEEXT 2768 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d r 0%"PRIo64"\n", sz, rcnt); DBG_TRACEEXT 2784 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); DBG_TRACEEXT 2861 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); DBG_TRACEEXT 3040 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpc tally %d c1 %03o c2 %03o\n", cpu.du.CHTALLY, c1, c2); DBG_TRACEEXT 3917 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 3920 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 3984 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 4011 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 4112 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 4115 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 4179 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 4207 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 4436 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, TA1, TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); DBG_TRACEEXT 4438 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, e -> TA1, e -> TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); DBG_TRACEEXT 4473 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #3\n"); DBG_TRACEEXT 4513 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #4\n"); DBG_TRACEEXT 4553 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #1\n"); DBG_TRACEEXT 4583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #2\n"); DBG_TRACEEXT 4848 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #1\n"); DBG_TRACEEXT 4879 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #2\n"); DBG_TRACEEXT 5042 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "src: %d: %o\n", n, c); DBG_TRACEEXT 5164 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 5166 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "inBuffer:"); DBG_TRACEEXT 5168 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, " %02o", * q); DBG_TRACEEXT 5169 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "\n"); DBG_TRACEEXT 5842 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "LTE IT[%d]<=%d\n", e -> mopIF - 1, next); DBG_TRACEEXT 5893 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC IF %d, srcTally %d, dstTally %d\n", e->mopIF, e->srcTally, e->dstTally); DBG_TRACEEXT 5896 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC n %d, srcTally %d, dstTally %d\n", n, e->srcTally, e->dstTally); DBG_TRACEEXT 5908 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC c %d (0%o)\n", c, c); DBG_TRACEEXT 5911 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES off\n"); DBG_TRACEEXT 5913 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is zero\n"); DBG_TRACEEXT 5920 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is not zero\n"); DBG_TRACEEXT 5934 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES on\n"); DBG_TRACEEXT 6004 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLS n %d c %o\n", n, c); DBG_TRACEEXT 6010 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is zero; edit insertion table entry 1 is moved to the receiving field in place of the character.\n"); DBG_TRACEEXT 6021 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is off; edit insertion table entry 3 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n"); DBG_TRACEEXT 6042 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is OFF; edit insertion table entry 4 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n"); DBG_TRACEEXT 6056 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is ON, the character is moved to the receiving field.\n"); DBG_TRACEEXT 6098 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MORS mopIF %d src %d dst %d\n", e->mopIF, e->srcTally, e->dstTally); DBG_TRACEEXT 6140 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC mopIF %d\n", e->mopIF); DBG_TRACEEXT 6144 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC n %d srcTally %d dstTally %d\n", n, e->srcTally, e->dstTally); DBG_TRACEEXT 6152 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC write to output buffer %o\n", *e->in); DBG_TRACEEXT 6161 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC done\n"); DBG_TRACEEXT 6492 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MOP %s(%o) %o\n", m -> mopName, mop, e->mopIF); DBG_TRACEEXT 6496 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "getMop(e->m == NULL || e->m->f == NULL): mop:%d IF:%d\n", mop, e->mopIF); DBG_TRACEEXT 6544 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor srcTally %d dstTally %d mopTally %d\n", e->srcTally, e->dstTally, e->mopTally); DBG_TRACEEXT 6548 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor EISgetMop forced break\n"); DBG_TRACEEXT 6573 src/dps8/dps8_eis.c DBG_TRACEEXT 6579 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 6599 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mop faults %o src %d dst %d mop %d\n", e->_faults, e->srcTally, e->dstTally, e->mopTally); DBG_TRACEEXT 6616 src/dps8/dps8_eis.c DBG_TRACEEXT 6632 src/dps8/dps8_eis.c DBG_TRACEEXT 6653 src/dps8/dps8_eis.c sim_debug(DBG_TRACEEXT, & cpu_dev, "mve\n"); DBG_TRACEEXT 6950 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 6954 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 7179 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 8030 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 8299 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 8303 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 8516 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 8686 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 8690 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 8890 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb N1 %d N2 %d\n", e -> N1, e -> N2); DBG_TRACEEXT 8917 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(min(e->N1, e->N2)) i %d b1 %d b2 %d\n", i, b1, b2); DBG_TRACEEXT 8937 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 < e->N2) i %d b1fill %d b2 %d\n", i, b1, b2); DBG_TRACEEXT 8957 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 > e->N2) i %d b1 %d b2fill %d\n", i, b1, b2); DBG_TRACEEXT 9720 src/dps8/dps8_eis.c DBG_TRACEEXT 9745 src/dps8/dps8_eis.c DBG_TRACEEXT 9756 src/dps8/dps8_eis.c DBG_TRACEEXT 9778 src/dps8/dps8_eis.c DBG_TRACEEXT 9799 src/dps8/dps8_eis.c DBG_TRACEEXT 9820 src/dps8/dps8_eis.c DBG_TRACEEXT 9840 src/dps8/dps8_eis.c DBG_TRACEEXT 9847 src/dps8/dps8_eis.c DBG_TRACEEXT 12376 src/dps8/dps8_eis.c DBG_TRACEEXT 12378 src/dps8/dps8_eis.c DBG_TRACEEXT 12407 src/dps8/dps8_eis.c DBG_TRACEEXT 12422 src/dps8/dps8_eis.c DBG_TRACEEXT 12425 src/dps8/dps8_eis.c DBG_TRACEEXT 12435 src/dps8/dps8_eis.c DBG_TRACEEXT 12441 src/dps8/dps8_eis.c DBG_TRACEEXT 12460 src/dps8/dps8_eis.c DBG_TRACEEXT 12550 src/dps8/dps8_eis.c DBG_TRACEEXT 12567 src/dps8/dps8_eis.c DBG_TRACEEXT 12589 src/dps8/dps8_eis.c DBG_TRACEEXT 12602 src/dps8/dps8_eis.c DBG_TRACEEXT 12616 src/dps8/dps8_eis.c DBG_TRACEEXT 12620 src/dps8/dps8_eis.c DBG_TRACEEXT 12627 src/dps8/dps8_eis.c DBG_TRACEEXT 12636 src/dps8/dps8_eis.c DBG_TRACEEXT 12679 src/dps8/dps8_eis.c DBG_TRACEEXT 12716 src/dps8/dps8_eis.c DBG_TRACEEXT 12734 src/dps8/dps8_eis.c DBG_TRACEEXT 12742 src/dps8/dps8_eis.c DBG_TRACEEXT 12924 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: clz1 %d clz2 %d\n",clz1,clz2); DBG_TRACEEXT 12930 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF2 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF2,NQ); DBG_TRACEEXT 12951 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv2d anomalous results"); } // divide by zero has already been checked before DBG_TRACEEXT 13004 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits); DBG_TRACEEXT 13015 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: addzero n2 %d %s exp %d\n",n2,res,op3->exponent); DBG_TRACEEXT 13352 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: clz1 %d clz2 %d\n",clz1,clz2); DBG_TRACEEXT 13358 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF3 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF3,NQ); DBG_TRACEEXT 13379 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv3d anomalous results"); } // divide by zero has already been checked before DBG_TRACEEXT 13432 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits); DBG_TRACEEXT 13443 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: addzero n3 %d %s exp %d\n",n3,res,op3->exponent); DBG_TRACEEXT 546 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); DBG_TRACEEXT 804 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); DBG_TRACEEXT 584 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\n", __func__, cpu.cu.XSF); DBG_TRACEEXT 1763 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400)); DBG_TRACEEXT 1764 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD CA %06o\n", cpu.TPR.CA); DBG_TRACEEXT 1790 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; offset is %06o\n", offset); DBG_TRACEEXT 1794 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]); DBG_TRACEEXT 1801 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]); DBG_TRACEEXT 2035 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta first %d rf %d rpt %d rd %d " "e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB); DBG_TRACEEXT 2045 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); DBG_TRACEEXT 2061 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); DBG_TRACEEXT 2073 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); DBG_TRACEEXT 2125 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally %d\n", x); DBG_TRACEEXT 2127 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally runout\n"); DBG_TRACEEXT 2131 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not tally runout\n"); DBG_TRACEEXT 2139 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is zero terminate\n"); DBG_TRACEEXT 2144 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not zero terminate\n"); DBG_TRACEEXT 2149 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is neg terminate\n"); DBG_TRACEEXT 2154 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not neg terminate\n"); DBG_TRACEEXT 2159 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is carry terminate\n"); DBG_TRACEEXT 2164 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not carry terminate\n"); DBG_TRACEEXT 2169 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is overflow terminate\n"); DBG_TRACEEXT 2182 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not terminate\n"); DBG_TRACEEXT 5641 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 6123 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 6778 src/dps8/dps8_ins.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) DBG_TRACEEXT 6797 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 6805 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, DBG_TRACEEXT 7229 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ldt TR %d (%o)\n", DBG_TRACEEXT 7279 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\n", cpu.rRALR); DBG_TRACEEXT 8405 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "entered DIS_cycle\n"); DBG_TRACEEXT 8432 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees an interrupt\n"); DBG_TRACEEXT 8449 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees a TRO\n"); DBG_TRACEEXT 8455 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS refetches\n"); DBG_TRACEEXT 1214 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fmp A %012"PRIo64" Q %012"PRIo64" E %03o\n", cpu.rA, cpu.rQ, cpu.rE); DBG_TRACEEXT 2308 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e1 %d %03o m1 %012"PRIo64" %012"PRIo64"\n", e1, e1, (word36) (m1 >> 36) & MASK36, (word36) m1 & MASK36); DBG_TRACEEXT 2323 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e2 %d %03o m2 %012"PRIo64" %012"PRIo64"\n", e2, e2, (word36) (m2 >> 36) & MASK36, (word36) m2 & MASK36); DBG_TRACEEXT 178 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b op1 %012"PRIo64" op2 %012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", op1, op2, carryin, flagsToSet, * flags); DBG_TRACEEXT 249 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b res %012"PRIo64" flags %06o ovf %o\n", res, * flags, * ovf); DBG_TRACEEXT 615 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", DBG_TRACEEXT 618 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", DBG_TRACEEXT 659 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", DBG_TRACEEXT 662 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", DBG_TRACEEXT 673 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf); DBG_TRACEEXT 675 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf); DBG_TRACEEXT 753 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf); DBG_TRACEEXT 755 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf); DBG_TRACEEXT 1091 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", op1.h, op1.l); DBG_TRACEEXT 1092 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", op2.h, op2.l); DBG_TRACEEXT 1095 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", op1s.h, op1s.l); DBG_TRACEEXT 1096 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", op2s.h, op2s.l); DBG_TRACEEXT 1098 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1>>64), (uint64_t) op1); DBG_TRACEEXT 1099 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2>>64), (uint64_t) op2); DBG_TRACEEXT 1102 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1s>>64), (uint64_t) op1s); DBG_TRACEEXT 1103 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2s>>64), (uint64_t) op2s);