dctrl 4336 src/dps8/dps8_cpu.c dbits &= dptr->dctrl; /* Look for just the bits that matched */ dctrl 4353 src/dps8/dps8_cpu.c if (sim_deb && dptr && (dptr->dctrl & dbits)) dctrl 30 src/dps8/dps8_simh.h (((dptr)->dctrl & (dbits)) || (dbits) == 0) && \ dctrl 32 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ dctrl 4001 src/simh/scp.c dptr->dctrl = flag ? (dptr->debflags ? flag : 0xFFFFFFFF) : 0;/* disable/enable w/o table */ dctrl 4004 src/simh/scp.c dptr->dctrl = dptr->dctrl | dep->mask; /* set all */ dctrl 4015 src/simh/scp.c dptr->dctrl = dptr->dctrl | dep->mask; dctrl 4016 src/simh/scp.c else dptr->dctrl = dptr->dctrl & ~dep->mask; dctrl 5067 src/simh/scp.c if (dptr->dctrl == 0) dctrl 5072 src/simh/scp.c uint32 dctrl = dptr->dctrl; dctrl 5075 src/simh/scp.c for (dep = dptr->debflags; (dctrl != 0) && (dep->name != NULL); dep++) { dctrl 5076 src/simh/scp.c if ((dctrl & dep->mask) == dep->mask) { dctrl 5077 src/simh/scp.c dctrl &= ~dep->mask; dctrl 9277 src/simh/scp.c if (sim_deb && exp->dptr && (exp->dptr->dctrl & exp->dbit)) { dctrl 9289 src/simh/scp.c if (sim_deb && exp->dptr && (exp->dptr->dctrl & exp->dbit)) { dctrl 9303 src/simh/scp.c if (sim_deb && exp->dptr && (exp->dptr->dctrl & exp->dbit)) { dctrl 9512 src/simh/scp.c dbits &= dptr->dctrl; /* Look for just the bits tha matched */ dctrl 9616 src/simh/scp.c if (sim_deb && dptr && (dptr->dctrl & dbits)) { dctrl 9762 src/simh/scp.c if (sim_deb && dptr && (dbits == 0 || (dptr->dctrl & dbits))) { dctrl 9828 src/simh/scp.c if (sim_deb && (dptr->dctrl & reason)) { dctrl 206 src/simh/scp.h # define sim_debug(dbits, dptr, ...) do { if ((sim_deb != NULL) && ((dptr != NULL) && ((dptr)->dctrl & dbits))) _sim_debug (dbits, dptr, __VA_ARGS__);} while (0) dctrl 1453 src/simh/sim_console.c (dptr->dctrl)) { dctrl 1461 src/simh/sim_console.c (dptr->dctrl)) { dctrl 347 src/simh/sim_defs.h uint32 dctrl; /* debug control */ dctrl 665 src/simh/sim_defs.h # define DEBUG_PRS(d) (sim_deb && d.dctrl) dctrl 666 src/simh/sim_defs.h # define DEBUG_PRD(d) (sim_deb && d->dctrl) dctrl 667 src/simh/sim_defs.h # define DEBUG_PRI(d,m) (sim_deb && (d.dctrl & (m))) dctrl 668 src/simh/sim_defs.h # define DEBUG_PRJ(d,m) (sim_deb && ((d)->dctrl & (m))) dctrl 385 src/simh/sim_disk.c uint32 save_dctrl = dptr->dctrl; dctrl 389 src/simh/sim_disk.c dptr->dctrl = 0xFFFFFFFF; dctrl 392 src/simh/sim_disk.c dptr->dctrl = save_dctrl; dctrl 942 src/simh/sim_disk.c uint32 save_dctrl = dptr->dctrl; dctrl 946 src/simh/sim_disk.c dptr->dctrl = 0xFFFFFFFF; dctrl 949 src/simh/sim_disk.c dptr->dctrl = save_dctrl; dctrl 1140 src/simh/sim_disk.c if (sim_deb && (ctx->dptr->dctrl & reason)) { dctrl 306 src/simh/sim_tape.c if (sim_deb && (ctx->dptr->dctrl & reason)) dctrl 815 src/simh/sim_tape.c sim_tape_data_trace(uptr, buf, rbc, "Record Read", ctx->dptr->dctrl & MTSE_DBG_DAT, MTSE_DBG_STR); dctrl 871 src/simh/sim_tape.c sim_tape_data_trace(uptr, buf, rbc, "Record Read Reverse", ctx->dptr->dctrl & MTSE_DBG_DAT, MTSE_DBG_STR); dctrl 909 src/simh/sim_tape.c sim_tape_data_trace(uptr, buf, bc, "Record Write", ctx->dptr->dctrl & MTSE_DBG_DAT, MTSE_DBG_STR); dctrl 946 src/simh/sim_tape.c sim_tape_data_trace(uptr, buf, sbc, "Record Written", ctx->dptr->dctrl & MTSE_DBG_DAT, MTSE_DBG_STR); dctrl 1919 src/simh/sim_tape.c if (sim_deb && (dptr->dctrl & MTSE_DBG_STR)) { dctrl 1921 src/simh/sim_tape.c sim_data_trace(dptr, uptr, ((dptr->dctrl & MTSE_DBG_DAT) ? recbuf : NULL), "", bc, "Data Record", MTSE_DBG_STR); dctrl 276 src/simh/sim_tmxr.h # define tmxr_debug(dbits, lp, msg, buf, bufsize) do {if (sim_deb && (lp)->mp && (lp)->mp->dptr && ((dbits) & (lp)->mp->dptr->dctrl)) _tmxr_debug (dbits, lp, msg, buf, bufsize); } while (0) dctrl 277 src/simh/sim_tmxr.h # define tmxr_debug_msg(dbits, lp, msg) do {if (sim_deb && (lp)->mp && (lp)->mp->dptr && ((dbits) & (lp)->mp->dptr->dctrl)) sim_debug (dbits, (lp)->mp->dptr, "%s", msg); } while (0) dctrl 278 src/simh/sim_tmxr.h # define tmxr_debug_return(lp, val) do {if (sim_deb && (val) && (lp)->mp && (lp)->mp->dptr && (TMXR_DBG_RET & (lp)->mp->dptr->dctrl)) { if ((lp)->rxbps) sim_debug (TMXR_DBG_RET, (lp)->mp->dptr, "Ln%d: 0x%x - Next after: %.0f\n", (int)((lp)-(lp)->mp->ldsc), val, (lp)->rxnexttime); else sim_debug (TMXR_DBG_RET, (lp)->mp->dptr, "Ln%d: 0x%x\n", (int)((lp)-(lp)->mp->ldsc), val); } } while (0) dctrl 279 src/simh/sim_tmxr.h # define tmxr_debug_trace(mp, msg) do {if (sim_deb && (mp)->dptr && (TMXR_DBG_TRC & (mp)->dptr->dctrl)) sim_debug (TMXR_DBG_TRC, mp->dptr, "%s\n", (msg)); } while (0) dctrl 280 src/simh/sim_tmxr.h # define tmxr_debug_trace_line(lp, msg) do {if (sim_deb && (lp)->mp && (lp)->mp->dptr && (TMXR_DBG_TRC & (lp)->mp->dptr->dctrl)) sim_debug (TMXR_DBG_TRC, (lp)->mp->dptr, "Ln%d:%s\n", (int)((lp)-(lp)->mp->ldsc), (msg)); } while (0) dctrl 281 src/simh/sim_tmxr.h # define tmxr_debug_connect(mp, msg) do {if (sim_deb && (mp)->dptr && (TMXR_DBG_CON & (mp)->dptr->dctrl)) sim_debug (TMXR_DBG_CON, mp->dptr, "%s\n", (msg)); } while (0) dctrl 282 src/simh/sim_tmxr.h # define tmxr_debug_connect_line(lp, msg) do {if (sim_deb && (lp)->mp && (lp)->mp->dptr && (TMXR_DBG_CON & (lp)->mp->dptr->dctrl)) sim_debug (TMXR_DBG_CON, (lp)->mp->dptr, "Ln%d:%s\n", (int)((lp)-(lp)->mp->ldsc), (msg)); } while (0)