cpt1U 2072 src/dps8/dps8_cpu.c CPT (cpt1U, 16); // LUF cpt1U 2454 src/dps8/dps8_cpu.c CPT (cpt1U, 0); // Interrupt cycle cpt1U 2475 src/dps8/dps8_cpu.c CPT (cpt1U, 1); // safe store complete cpt1U 2492 src/dps8/dps8_cpu.c CPT (cpt1U, 2); // interrupt pending cpt1U 2501 src/dps8/dps8_cpu.c CPT (cpt1U, 3); // interrupt identified cpt1U 2515 src/dps8/dps8_cpu.c CPT (cpt1U, 4); // interrupt pair fetched cpt1U 2524 src/dps8/dps8_cpu.c CPT (cpt1U, 5); // interrupt pair spurious cpt1U 2542 src/dps8/dps8_cpu.c CPT (cpt1U, 13); // fetch cycle cpt1U 2608 src/dps8/dps8_cpu.c CPT (cpt1U, 14); // sampling interrupts cpt1U 2675 src/dps8/dps8_cpu.c CPT (cpt1U, 15); // interrupt cpt1U 2724 src/dps8/dps8_cpu.c cpt1U 2762 src/dps8/dps8_cpu.c CPT (cpt1U, 20); // not XEC or RPx cpt1U 2778 src/dps8/dps8_cpu.c CPT (cpt1U, 21); // go to exec cycle cpt1U 2921 src/dps8/dps8_cpu.c CPT (cpt1U, 22); // exec cycle cpt1U 2948 src/dps8/dps8_cpu.c CPT (cpt1U, 23); // execution complete cpt1U 2963 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 2978 src/dps8/dps8_cpu.c CPT (cpt1U, 24); // transfer instruction cpt1U 2996 src/dps8/dps8_cpu.c CPT (cpt1U, 9); // nbar set cpt1U 3005 src/dps8/dps8_cpu.c CPT (cpt1U, 10); // temporary absolute mode cpt1U 3036 src/dps8/dps8_cpu.c CPT (cpt1U, 25); // DIS instruction cpt1U 3216 src/dps8/dps8_cpu.c CPT (cpt1U, 26); // RPx instruction cpt1U 3230 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3255 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3284 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 3328 src/dps8/dps8_cpu.c CPT (cpt1U, 28); // enter fetch cycle cpt1U 3336 src/dps8/dps8_cpu.c CPT (cpt1U, 29); // sync. fault return cpt1U 3350 src/dps8/dps8_cpu.c CPT (cpt1U, 30); // fault cycle cpt1U 3395 src/dps8/dps8_cpu.c CPT (cpt1U, 31); // safe store complete cpt1U 3435 src/dps8/dps8_cpu.c CPT (cpt1U, 33); // set fault exec cycle cpt1U 1902 src/dps8/dps8_cpu.h #define cpt1U 0 // Instruction processing tracking