IR 4095 src/dps8/dps8_cpu.c putbits36_1 (& w0, 17, TSTF (cpu.cu.IR, I_NBAR)?1:0); IR 988 src/dps8/dps8_cpu.h word18 IR; // 18-35 Indicator register IR 581 src/dps8/dps8_hw_consts.h # define CLR_I_ABS CLRF (cpu.cu.IR, I_ABS) IR 582 src/dps8/dps8_hw_consts.h # define CLR_I_MIF CLRF (cpu.cu.IR, I_MIF) IR 583 src/dps8/dps8_hw_consts.h # define CLR_I_TRUNC CLRF (cpu.cu.IR, I_TRUNC) IR 584 src/dps8/dps8_hw_consts.h # define CLR_I_NBAR CLRF (cpu.cu.IR, I_NBAR) IR 585 src/dps8/dps8_hw_consts.h # define CLR_I_TALLY CLRF (cpu.cu.IR, I_TALLY) IR 586 src/dps8/dps8_hw_consts.h # define CLR_I_PMASK CLRF (cpu.cu.IR, I_PMASK) IR 587 src/dps8/dps8_hw_consts.h # define CLR_I_EOFL CLRF (cpu.cu.IR, I_EOFL) IR 588 src/dps8/dps8_hw_consts.h # define CLR_I_EUFL CLRF (cpu.cu.IR, I_EUFL) IR 589 src/dps8/dps8_hw_consts.h # define CLR_I_OFLOW CLRF (cpu.cu.IR, I_OFLOW) IR 590 src/dps8/dps8_hw_consts.h # define CLR_I_CARRY CLRF (cpu.cu.IR, I_CARRY) IR 591 src/dps8/dps8_hw_consts.h # define CLR_I_NEG CLRF (cpu.cu.IR, I_NEG) IR 592 src/dps8/dps8_hw_consts.h # define CLR_I_ZERO CLRF (cpu.cu.IR, I_ZERO) IR 594 src/dps8/dps8_hw_consts.h # define SET_I_ABS SETF (cpu.cu.IR, I_ABS) IR 595 src/dps8/dps8_hw_consts.h # define SET_I_NBAR SETF (cpu.cu.IR, I_NBAR) IR 596 src/dps8/dps8_hw_consts.h # define SET_I_TRUNC SETF (cpu.cu.IR, I_TRUNC) IR 597 src/dps8/dps8_hw_consts.h # define SET_I_TALLY SETF (cpu.cu.IR, I_TALLY) IR 598 src/dps8/dps8_hw_consts.h # define SET_I_EOFL SETF (cpu.cu.IR, I_EOFL) IR 599 src/dps8/dps8_hw_consts.h # define SET_I_EUFL SETF (cpu.cu.IR, I_EUFL) IR 600 src/dps8/dps8_hw_consts.h # define SET_I_OFLOW SETF (cpu.cu.IR, I_OFLOW) IR 601 src/dps8/dps8_hw_consts.h # define SET_I_CARRY SETF (cpu.cu.IR, I_CARRY) IR 602 src/dps8/dps8_hw_consts.h # define SET_I_NEG SETF (cpu.cu.IR, I_NEG) IR 603 src/dps8/dps8_hw_consts.h # define SET_I_ZERO SETF (cpu.cu.IR, I_ZERO) IR 605 src/dps8/dps8_hw_consts.h # define TST_I_ABS TSTF (cpu.cu.IR, I_ABS) IR 606 src/dps8/dps8_hw_consts.h # define TST_I_MIF TSTF (cpu.cu.IR, I_MIF) IR 607 src/dps8/dps8_hw_consts.h # define TST_I_NBAR TSTF (cpu.cu.IR, I_NBAR) IR 608 src/dps8/dps8_hw_consts.h # define TST_I_PMASK TSTF (cpu.cu.IR, I_PMASK) IR 609 src/dps8/dps8_hw_consts.h # define TST_I_TRUNC TSTF (cpu.cu.IR, I_TRUNC) IR 610 src/dps8/dps8_hw_consts.h # define TST_I_TALLY TSTF (cpu.cu.IR, I_TALLY) IR 611 src/dps8/dps8_hw_consts.h # define TST_I_OMASK TSTF (cpu.cu.IR, I_OMASK) IR 612 src/dps8/dps8_hw_consts.h # define TST_I_EUFL TSTF (cpu.cu.IR, I_EUFL ) IR 613 src/dps8/dps8_hw_consts.h # define TST_I_EOFL TSTF (cpu.cu.IR, I_EOFL ) IR 614 src/dps8/dps8_hw_consts.h # define TST_I_OFLOW TSTF (cpu.cu.IR, I_OFLOW) IR 615 src/dps8/dps8_hw_consts.h # define TST_I_CARRY TSTF (cpu.cu.IR, I_CARRY) IR 616 src/dps8/dps8_hw_consts.h # define TST_I_NEG TSTF (cpu.cu.IR, I_NEG) IR 617 src/dps8/dps8_hw_consts.h # define TST_I_ZERO TSTF (cpu.cu.IR, I_ZERO) IR 618 src/dps8/dps8_hw_consts.h # define TST_I_HEX TSTF (cpu.cu.IR, I_HEX) IR 620 src/dps8/dps8_hw_consts.h # define SC_I_HEX(v) SCF (v, cpu.cu.IR, I_HEX) // DPS8M only IR 621 src/dps8/dps8_hw_consts.h # define SC_I_MIF(v) SCF (v, cpu.cu.IR, I_MIF) IR 622 src/dps8/dps8_hw_consts.h # define SC_I_TALLY(v) SCF (v, cpu.cu.IR, I_TALLY) IR 623 src/dps8/dps8_hw_consts.h # define SC_I_NEG(v) SCF (v, cpu.cu.IR, I_NEG) IR 624 src/dps8/dps8_hw_consts.h # define SC_I_ZERO(v) SCF (v, cpu.cu.IR, I_ZERO) IR 625 src/dps8/dps8_hw_consts.h # define SC_I_CARRY(v) SCF (v, cpu.cu.IR, I_CARRY); IR 626 src/dps8/dps8_hw_consts.h # define SC_I_OFLOW(v) SCF (v, cpu.cu.IR, I_OFLOW); IR 627 src/dps8/dps8_hw_consts.h # define SC_I_EOFL(v) SCF (v, cpu.cu.IR, I_EOFL); IR 628 src/dps8/dps8_hw_consts.h # define SC_I_EUFL(v) SCF (v, cpu.cu.IR, I_EUFL); IR 629 src/dps8/dps8_hw_consts.h # define SC_I_OMASK(v) SCF (v, cpu.cu.IR, I_OMASK); IR 630 src/dps8/dps8_hw_consts.h # define SC_I_PERR(v) SCF (v, cpu.cu.IR, I_PERR); IR 631 src/dps8/dps8_hw_consts.h # define SC_I_PMASK(v) SCF (v, cpu.cu.IR, I_PMASK); IR 632 src/dps8/dps8_hw_consts.h # define SC_I_TRUNC(v) SCF (v, cpu.cu.IR, I_TRUNC); IR 403 src/dps8/dps8_ins.c putbits36_18 (& words[4], 18, cpu.cu.IR); IR 655 src/dps8/dps8_ins.c cpu.cu.IR = getbits36_18 (words[4], 18); // HWR IR 2200 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\n", cpu.rA, cpu.rQ, dump_flags (buf, cpu.cu.IR)); IR 2722 src/dps8/dps8_ins.c cmp36 (cpu.rQ, cpu.CY, &cpu.cu.IR); IR 2934 src/dps8/dps8_ins.c cmp36 (cpu.rA, cpu.CY, &cpu.cu.IR); IR 2947 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); IR 2983 src/dps8/dps8_ins.c if (! (cpu.cu.IR & I_NEG) && ! (cpu.cu.IR & I_ZERO)) IR 3231 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); IR 3243 src/dps8/dps8_ins.c if (cpu.cu.IR & (I_NEG | I_ZERO)) IR 3390 src/dps8/dps8_ins.c DPS8M_ (cpu.CY = cpu.cu.IR & 0000000777770LL; ) IR 3392 src/dps8/dps8_ins.c L68_ (cpu.CY = cpu.cu.IR & 0000000777760LL;) IR 3395 src/dps8/dps8_ins.c cpu.CY = cpu.cu.IR & 0000000777600LL; IR 3441 src/dps8/dps8_ins.c cpu.rA = compl36 (cpu.CY, & cpu.cu.IR, & ovf); IR 3452 src/dps8/dps8_ins.c cpu.rQ = compl36 (cpu.CY, & cpu.cu.IR, & ovf); IR 3472 src/dps8/dps8_ins.c cpu.rX[n] = compl18 (GETHI (cpu.CY), & cpu.cu.IR, & ovf); IR 3769 src/dps8/dps8_ins.c DPS8M_ (SETLO (cpu.CY, cpu.cu.IR & 0777770);) IR 3770 src/dps8/dps8_ins.c L68_ (SETLO (cpu.CY, cpu.cu.IR & 0777760);) IR 4229 src/dps8/dps8_ins.c cpu.rA = Add36b (cpu.rA, cpu.CY, 0, I_ZNOC, & cpu.cu.IR, & ovf); IR 4248 src/dps8/dps8_ins.c tmp72, 0, I_ZNOC, & cpu.cu.IR, & ovf); IR 4269 src/dps8/dps8_ins.c tmp72, 0, I_ZNOC, & cpu.cu.IR, & ovf); IR 4294 src/dps8/dps8_ins.c tmp72, 0, I_ZNC, & cpu.cu.IR, & ovf); IR 4315 src/dps8/dps8_ins.c cpu.rA = Add36b (cpu.rA, cpu.CY, 0, I_ZNC, & cpu.cu.IR, & ovf); IR 4334 src/dps8/dps8_ins.c cpu.rQ = Add36b (cpu.rQ, cpu.CY, 0, I_ZNC, & cpu.cu.IR, & ovf); IR 4358 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); IR 4386 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); IR 4407 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); IR 4420 src/dps8/dps8_ins.c cpu.CY = Add36b (cpu.rQ, cpu.CY, 0, I_ZNOC, & cpu.cu.IR, & ovf); IR 4444 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); IR 4461 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); IR 4480 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); IR 4499 src/dps8/dps8_ins.c cpu.rA = Sub36b (cpu.rA, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); IR 4518 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, IR 4538 src/dps8/dps8_ins.c cpu.rA = Sub36b (cpu.rA, cpu.CY, 1, I_ZNC, & cpu.cu.IR, & ovf); IR 4562 src/dps8/dps8_ins.c I_ZNC, & cpu.cu.IR, & ovf); IR 4579 src/dps8/dps8_ins.c cpu.rQ = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNC, & cpu.cu.IR, & ovf); IR 4606 src/dps8/dps8_ins.c I_ZNC, & cpu.cu.IR, & ovf); IR 4621 src/dps8/dps8_ins.c cpu.rQ = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); IR 4649 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); IR 4666 src/dps8/dps8_ins.c cpu.CY = Sub36b (cpu.rA, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); IR 4680 src/dps8/dps8_ins.c cpu.CY = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); IR 4705 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); IR 4722 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); IR 4741 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); IR 5152 src/dps8/dps8_ins.c cmp72 (trAQ, tmp72, &cpu.cu.IR); IR 5175 src/dps8/dps8_ins.c cmp18 (cpu.rX[n], GETHI (cpu.CY), &cpu.cu.IR); IR 5191 src/dps8/dps8_ins.c cmp36wl (cpu.rA, cpu.CY, cpu.rQ, &cpu.cu.IR); IR 6164 src/dps8/dps8_ins.c cpu.cu.IR = tempIR; IR 601 src/dps8/dps8_math.c m3 = Add72b (m1, m2, 0, I_CARRY, & cpu.cu.IR, & ovf); IR 2124 src/dps8/dps8_math.c word72 m3 = Add72b (m1, m2, 0, I_CARRY, & cpu.cu.IR, & ovf); IR 29 src/dps8/dps8_mp.h word36 A, Q, E, X [8], IR, TR, RALR; IR 4088 src/dps8/dps8_sys.c { "cpus[].cu.IR", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (ctl_unit_data_t, IR) }, IR 108 src/dps8/hdbg.h # define HDBGRegIR(c) hdbgRegW (hreg_IR, (word36) cpu.cu.IR, c)