switches 181 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.FLT_BASE); switches 183 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.cpu_num); switches 185 src/dps8/dps8_cpu.c (unsigned long long)cpus[cpu_unit_idx].switches.data_switches); switches 187 src/dps8/dps8_cpu.c PBI_64((unsigned long long)cpus[cpu_unit_idx].switches.data_switches)); switches 191 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches); switches 193 src/dps8/dps8_cpu.c PBI_32(cpus[cpu_unit_idx].switches.addr_switches)); switches 199 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); switches 201 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.init_enable [i]); switches 203 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.assignment [i]); switches 205 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.interlace [i]); switches 207 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.store_size [i]); switches 210 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode == \ switches 211 src/dps8/dps8_cpu.c procModeMultics ? "Multics" : cpus[cpu_unit_idx].switches.procMode == procModeGCOS ? "GCOS" : "???", switches 212 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode); switches 214 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable_cache ? "Enabled" : "Disabled"); switches 216 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.sdwam_enable ? "Enabled" : "Disabled"); switches 218 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.ptwam_enable ? "Enabled" : "Disabled"); switches 506 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.FLT_BASE = (uint) v; switches 508 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.cpu_num = (uint) v; switches 510 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = (word36) v; switches 524 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = d; switches 527 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches = (word18) v; switches 529 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode = v ? procModeMultics : procModeGCOS; switches 540 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [port_num] = (uint) v; switches 542 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [port_num] = (uint) v; switches 544 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; switches 546 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [port_num] = (uint) v; switches 573 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [port_num] = (uint) v; switches 576 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable_cache = (uint) v ? true : false; switches 578 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.sdwam_enable = (uint) v ? true : false; switches 580 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.ptwam_enable = (uint) v ? true : false; switches 629 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].isolts_switches_save = cpus[cpu_unit_idx].switches; switches 631 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = 00000030714000; switches 632 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches = 0100150; switches 635 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [0] = 0; switches 636 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [0] = false; switches 637 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; switches 638 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [0] = false; switches 639 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [0] = store_sz; switches 641 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [1] = 0; switches 642 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [1] = false; switches 643 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; switches 644 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [1] = false; switches 645 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [1] = store_sz; switches 647 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [2] = 0; switches 648 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [2] = false; switches 649 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; switches 650 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [2] = false; switches 651 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [2] = store_sz; switches 653 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [3] = 0; switches 654 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [3] = false; switches 655 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; switches 656 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [3] = false; switches 657 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [3] = store_sz; switches 660 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [4] = 0; switches 661 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [4] = false; switches 662 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; switches 663 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [4] = false; switches 664 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [4] = 3; switches 666 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [5] = 0; switches 667 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [5] = false; switches 668 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; switches 669 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [5] = false; switches 670 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [5] = 3; switches 672 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [6] = 0; switches 673 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [6] = false; switches 674 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; switches 675 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [6] = false; switches 676 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [6] = 3; switches 678 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [7] = 0; switches 679 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [7] = false; switches 680 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; switches 681 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [7] = false; switches 682 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [7] = 3; switches 684 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; //-V1048 switches 700 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches = cpus[cpu_unit_idx].isolts_switches_save; switches 861 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = port_num; switches 862 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 863 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 2; switches 864 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; switches 865 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 1; switches 868 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = 0; switches 869 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 870 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 0; switches 871 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; switches 872 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 0; switches 886 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = port_num; switches 887 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 888 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 7; switches 889 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; switches 890 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 1; switches 893 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = 0; switches 894 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 895 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 0; switches 896 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; switches 897 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 0; switches 987 src/dps8/dps8_cpu.c cpu.cu.SD_ON = cpu.switches.sdwam_enable ? 1 : 0; switches 988 src/dps8/dps8_cpu.c cpu.cu.PT_ON = cpu.switches.ptwam_enable ? 1 : 0; switches 1322 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) switches 1334 src/dps8/dps8_cpu.c uint store_size = cpu.switches.store_size [port_num]; switches 1364 src/dps8/dps8_cpu.c uint base_addr_wds = sz_wds * cpu.switches.assignment[port_num]; switches 1440 src/dps8/dps8_cpu.c if (cpu.switches.serno) switches 1442 src/dps8/dps8_cpu.c cpu.switches.serno = sn; switches 1445 src/dps8/dps8_cpu.c sim_msg ("%s CPU serial number: %u\r\n", sim_name, cpu.switches.serno); switches 1453 src/dps8/dps8_cpu.c if (cpus[cpun].switches.serno) switches 1455 src/dps8/dps8_cpu.c cpus[cpun].switches.serno = sn; switches 1459 src/dps8/dps8_cpu.c sim_name, cpun, cpus[cpun].switches.serno); switches 1835 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.switches.data_switches; switches 3425 src/dps8/dps8_cpu.c uint fltAddress = (cpu.switches.FLT_BASE << 5) & 07740; switches 4875 src/dps8/dps8_cpu.c putbits36_3 (& rsw2, 33, cpus[cpuNo].switches.cpu_num & 07LL); switches 4885 src/dps8/dps8_cpu.c (void)sprintf (serial, "%-11u", cpus[cpuNo].switches.serno); switches 5406 src/dps8/dps8_cpu.c cpus[i].switches.FLT_BASE = 2; // Some of the UnitTests assume this switches 1630 src/dps8/dps8_cpu.h switches_t switches; switches 422 src/dps8/dps8_ins.c putbits36_3 (& words[2], 27, (word3) cpu.switches.cpu_num); switches 3556 src/dps8/dps8_ins.c if (cpu.switches.procMode == procModeGCOS) switches 8234 src/dps8/dps8_ins.c cpu.rA = cpu.switches.data_switches; switches 8265 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [0] & 07LL) switches 8267 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) switches 8269 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [0] & 01LL) switches 8271 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] ? 1LL:0LL) switches 8273 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [0] & 07LL) switches 8276 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [1] & 07LL) switches 8278 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) switches 8280 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [1] & 01LL) switches 8282 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] ? 1LL:0LL) switches 8284 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [1] & 07LL) switches 8287 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [2] & 07LL) switches 8289 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) switches 8291 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [2] & 01LL) switches 8293 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] ? 1LL:0LL) switches 8295 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [2] & 07LL) switches 8298 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [3] & 07LL) switches 8300 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) switches 8302 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [3] & 01LL) switches 8304 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] ? 1LL:0LL) switches 8306 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [3] & 07LL) switches 8379 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[0] == 2 ? switches 8381 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[1] == 2 ? switches 8383 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[2] == 2 ? switches 8385 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[3] == 2 ? switches 8397 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.FLT_BASE & 0177LL) switches 8422 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.enable_cache ? 1 : 0) switches 8427 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.procMode) /* 0b1 DPS8M */ switches 8429 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.procMode & 1U) switches 8451 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.cpu_num & 07LL) switches 8488 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [4] & 07LL) switches 8490 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) switches 8492 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [4] & 01LL) switches 8494 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] ? 1LL:0LL) switches 8496 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [4] & 07LL) switches 8499 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [5] & 07LL) switches 8501 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) switches 8503 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [5] & 01LL) switches 8505 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] ? 1LL:0LL) switches 8507 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [5] & 07LL) switches 8510 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [6] & 07LL) switches 8512 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) switches 8514 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [6] & 01LL) switches 8516 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] ? 1LL:0LL) switches 8518 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [6] & 07LL) switches 8521 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [7] & 07LL) switches 8523 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL) switches 8525 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [7] & 01LL) switches 8527 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] ? 1LL:0LL) switches 8529 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [7] & 07LL) switches 8550 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] == 2 ? switches 8552 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] == 2 ? switches 8554 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] == 2 ? switches 8556 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] == 2 ? switches 8559 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] == 2 ? switches 8561 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] == 2 ? switches 8563 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] == 2 ? switches 8565 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] == 2 ? switches 428 src/dps8/panelScraper.c SETL (bank_a, 27+3, (word3) cpu.switches.cpu_num, 3); switches 1396 src/dps8/panelScraper.c SETS (cpu.switches.data_switches, port_data, 0, 36); switches 1400 src/dps8/panelScraper.c SETS (cpu.switches.addr_switches, port_data, 0, 18); switches 9902 src/simh/scp.c t_stat sim_exp_set (EXPECT *exp, const char *match, int32 cnt, uint32 after, int32 switches, const char *act) switches 9913 src/simh/scp.c if (switches & EXP_TYP_REGEX) { switches 9918 src/simh/scp.c if (switches & EXP_TYP_REGEX_I) { switches 9931 src/simh/scp.c (exp->rules[i].switches & EXP_TYP_PERSIST)) switches 9957 src/simh/scp.c ep->switches = switches; /* set switches */ switches 9964 src/simh/scp.c if (switches & EXP_TYP_REGEX) { switches 10002 src/simh/scp.c size_t compare_size = (exp->rules[i].switches & EXP_TYP_REGEX) ? MAX(10 * strlen(ep->match_pattern), 1024) : exp->rules[i].size; switches 10018 src/simh/scp.c if (ep->switches & EXP_TYP_PERSIST) switches 10020 src/simh/scp.c if (ep->switches & EXP_TYP_CLEARALL) switches 10022 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX) switches 10024 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX_I) switches 10103 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX) { switches 10171 src/simh/scp.c int32 switches = ep->switches; switches 10179 src/simh/scp.c if (ep->switches & EXP_TYP_CLEARALL) /* Clear-all expect rule? */ switches 10182 src/simh/scp.c if (!(ep->switches & EXP_TYP_PERSIST)) /* One shot expect rule? */ switches 10186 src/simh/scp.c (switches & EXP_TYP_TIME) ? switches 189 src/simh/scp.h t_stat sim_exp_set (EXPECT *exp, const char *match, int32 cnt, uint32 after, int32 switches, const char *act); switches 633 src/simh/scp.h const char *switches, switches 630 src/simh/sim_defs.h int32 switches; /* flags */