1 06/18/88 MAKE
2
3 Name:
4
5 make -- maintain, update, and regenerate groups of programs
6
7
8 Synopsis:
9
10 make -f makefile -piksrnbemtdq names
11
12
13 Description:
14
15 The following is a brief description of all options and some special
16 names.
17
18 -f MAKEFILE Description file name. MAKEFILE is assumed to be the
19 name of a description file. A file name of - denotes
20 the standard input. The contents of MAKEFILE override
21 the built-in rules if they are present.
22
23 -p Print out the complete set of macro definitions and
24 target descriptions.
25
26
27 -i Ignore error codes returned by invoked commands. This
28 mode is entered if the fake target name .IGNORE appears
29 in the description file.
30
31 -k Abandon work on the current entry, but continue on other
32 branches that do not depend on that entry.
33
34 -s Silent mode. Do not print command lines before
35 executing. This mode is also entered if the fake target
36 name .SILENT appears in the description file.
37
38 -r Do not use the built-in rules.
39
40 -n No execute mode. Print commands, but do not execute
41 them. Even lines beginning with an @ are printed.
42
43
44 -b Compatibility mode for old makefiles.
45
46 -e Environment variables override assignments within
47 makefiles.
48
49 -t Touch the target files causing them to be up-to-date
50 rather than issue the usual commands.
51
52 -d Debug mode. Print out detailed information on files
53 and times examined.
54
55
56 -q Question. The MAKE command returns a zero or non-zero
57 status code depending on whether the target file is or
58 is not up-to-date.
59
60
61 .DEFAULT If a file must be made but there are no explicit commands
62 or relevant built-in rules, the commands associated with
63 the name .DEFAULT are used it it exists.
64
65 .PRECIOUS Dependents of this target will not be removed when quit
66 or interrupt are hit.
67
68 .SILENT Same effect as the -s option.
69
70 .IGNORE Same effect as the -i option.
71
72
73 MAKE executes commands in MAKEFILE to update one or more target NAMES.
74 NAME is typically a program. If no -f option is present, "makefile",
75 and then "Makefile" are tried in order. If MAKEFILE is -, the
76 standard input is taken. More than one - MAKEFILE argument pair may
77 appear.
78
79 MAKE updates a target only if its dependents are newer than the
80 target. All prerequisite files of a target are added recursively to
81 the list of targets. Missing files are deemed to be out-of-date.
82
83
84 MAKEFILE contains a sequence of entries that specify dependencies.
85 The first line of an entry is a blank-separated, non-null list of
86 targets, then a :, then a possibly null list of prerequisite files
87 or dependencies. Text following a ; and all following lines that
88 begin with a tab are commands to be executed to update the target.
89 The first line that does not begin with a tab or # begins a new
90 dependency or macro definition. Commands may be continued across
91 lines with the <backslash><new-line> sequence. Everything printed by
92 MAKE except the initial tab is passed directly to the command
93 processor. Thus,
94
95 echo a\
96 b
97 will produce
98 ab
99
100 Sharp# and new-line surround comments.
101
102
103 The following MAKEFILE says that pgm depends on two files a.cob and b.cob,
104 and that they in turn depend on their corresponding source files a.c
105 and b.c and a common file incl.h.
106
107 pgm: a.cob b.cob
108 cc a.cob b.cob -of pgm
109 a.cob: incl.h a.c
110 cc a.c -spaf alm
111 b.cob: incl.h b.c
112 cc b.c -spaf alm
113
114
115 Command lines are executed one at a time. The first one or two
116 characters in a command can be the following: -, @, -@, or @-. If @
117 is present, printing of the command is suppressed. If - is present,
118 MAKE ignores an error. A line is printed when it is executed unless
119 the -s option is present, or the entry .SILENT: is in MAKEFILE, or
120 unless the initial character sequence contains a @. The -n options
121 specifies printing without execution; however, if the command line has
122 the string $MAKE in it, the line is always executed see discussion
123 of the MAKEFLAGS macro under "Environment". The -t touch option
124 updates the modified date of a file without executing any commands.
125 See the documentation for the TOUCH command.
126
127
128 Commands returning non-zero status normally terminate MAKE. If the -i
129 option is present, or the entry .IGNORE: appears in MAKEFILE, or the
130 initial character sequence of the command contains -, the error is
131 ignored. If the -k option is present, work is abandoned on the
132 current entry, but continues on other branches that do not depend on
133 that entry.
134
135 The -b option allows old makefiles those written for the old version
136 of MAKE to run without errors. The difference between the old
137 version of MAKE and this version is that this version requires all
138 dependency lines to have a possibly null or implicit command
139 associated with them. The previous version of MAKE assumed, if no
140 command was specified explicitly, that the command was null.
141
142
143 Environment:
144
145 The environment is read by MAKE. All variables are assumed to be
146 macro definitions and processed as such. The environment variables
147 are processed before any makefile and after the internal rules; thus,
148 macro assignments in a makefile override environment variables. The
149 -e option causes the environment to override the macro assignments in
150 a makefile.
151
152
153 The MAKEFLAGS environment variable is processed by MAKE as containing
154 any legal input option except -f -p and -d defined for the command
155 line. Further, upon invocation, MAKE "invents" the variable if it is
156 not in the environment, puts the current options into it, and passes
157 it on to invocation of commands. Thus, MAKEFLAGS always contains the
158 current input options. This proves very useful for "super-makes". In
159 fact, as noted above, when the -n option is used, the command $MAKE
160 is executed anyway; hence, one can perform a make -n recursively on a
161 whole software system to see what would have been executed. This is
162 because the -n is put in MAKEFLAGS and passed to further invocations
163 of $MAKE. This is one way of debugging all of the makefiles for a
164 software project without actually doing anything.
165
166
167 Macros:
168
169 Entries of the form string1=string2 are macro definitions. String2 is
170 defined as all characters up to a comment character or an unescaped
171 new-line. Subsequent appearances of $string1:subst1=subst2 are
172 replaced by string2. The parentheses are optional if a single
173 character macro name is used and there is no substitute sequence. If
174 it is specified, all non-overlapping occurrences of subst1 in the
175 named macro are replaced by subst2. Strings for the purposes of this
176 type of substitution are delimited by blanks, tabs, new-line
177 characters, and beginnings of lines.
178
179
180 Internal macros:
181
182 There are five internally maintained macros which are useful for
183 writing rules for building targets.
184
185 $* The macro $* stands for the file name part of the current
186 dependent with the suffix deleted. It is evaluated only for
187 inference rules.
188
189 $@ The $@ macro stands for the full target name of the current target.
190 It is evaluated only for explicitly named dependencies.
191
192
193 $< The $< macro is only evaluated for inference rules or the .DEFAULT
194 rule. It is the module which is out-of-date with respect to the
195 target i.e. the "manufactured" dependent file name. Thus, in
196 the .c.cob rule, the $< macro would evaluate to the .c file. An
197 example for making .cob files from .c files is
198
199 .c.cob:
200 cc $*.c -spaf alm
201 OR
202 .c.cob:
203 cc $< -spaf alm
204
205
206 $? The $? macro is evaluated when explicit rules from the makefile
207 are evaluated. It is the list of prerequisites that are
208 out-of-date with respect to the target; essentially, those modules
209 which must be rebuilt.
210
211 $% The $% macro is only evaluated when the target is an archive
212 library member of the form libfile.cob. In this case, $@
213 evaluates to lib and $% evaluates to the library member, file.cob.
214
215 Four of the five macros can have alternative forms. When an upper
216 case D or F is appended to any of the four macros, the meaning is
217 changed to "directory part" for D and "file part" for F. Thus, $@D
218 refers to the directory part of the string $@. If there is no
219 directory part, the working directory is generated. The only macro
220 excluded from this alternative form is $?. The reasons for this are
221 debatable.
222
223
224 Suffixes:
225
226 Certain names for instance those ending with .cob have inferable
227 prerequisites such as .c, etc. If no update commands for such a file
228 appear in MAKEFILE, and if an inferable prerequisite exists, that
229 prerequisite is compiled to make the target. In this case, MAKE has
230 inference rules which allow building files from other files by
231 examining the suffixes and determining an appropriate inference rule
232 to use. The current default inference rules are
233
234 .c, .c.cob, .alm.cob, .y.cob, .l.cob, .y.c, .l.c
235
236
237 A rule with only one suffix i.e. .c is the definition of how to
238 build x from x.c. In effect, the other suffix is null. This is
239 useful for building targets from only one source file e.g. shell
240 procedures simple C programs.
241
242
243 Additional suffixes are given as the dependency list for .SUFFIXES.
244 Order is significant; the first possible name for which both a file
245 and a rule exist is inferred as a prerequisite. The default list is
246
247 .SUFFIXES: .cob .c .y .l .alm .h
248
249 Multiple suffix lists can accumulate. To clear the suffix list,
250 define a target .SUFFIXES which has no dependencies. Note that the
251 suffix .o has been replaced by .cob, and that .alm replaces .s. See
252 the documentation for the C compiler cc.
253
254
255 Inference Rules:
256
257 The first example can be done more briefly.
258
259 pgm: a.cob b.cob
260 cc a.cob b.cob -of pgm
261 a.cob b.cob: incl.h
262
263 This is because MAKE has a set of internal rules for building files.
264 The user may add rules to this list by simply putting them in the
265 MAKEFILE. Such as rules for building PL/1 objects
266
267
268 Certain macros are used by the default inference rules to permit the
269 inclusion of optional matter in any resulting commands. For example,
270 CFLAGS, LFLAGS, and YFLAGS are used for compiler options to the C
271 compiler, LEX, and YACC, respectively.
272
273 The inference of prerequisites can be controlled. The rule to create
274 a file with suffix .cob from a file with suffix .c is specified as an
275 entry with .c.cob: as the target and no dependents. Commands
276 associated with the target define the rule for making a .cob file from
277 a .c file. Any target that has no ">" in it and starts with a dot
278 is identified as a rule and not a true target.
279
280
281 DIFFERENCES:
282
283 The following is a summary of the differences between between the
284 Multics version of MAKE and a typical Unix version.
285
286 Unix-type archive libraries are not supported on Multics. Thus,
287 makefiles containing library references such as $LIBfile.o are
288 illegal. The internal rules and suffixes supporting these have not
289 been implemented.
290
291 Unix-type SCCS Source Code Control System files are not supported.
292 Again, the internal rules and suffixes supporting this have not been
293 implemented. The GET macro is still defined as "get" but no such
294 Multics command exists.
295
296 Multics search rules, rather than the environment variable PATH is
297 used to find commands.
298
299
300 Commands are passed directly to the command processor. This creates
301 several differences.
302
303 * Active functions and abbrevs used in commands are expanded.
304
305 * Each command is NOT executed in a separate subshell, so
306 commands that alter the environment such as cwd may affect
307 later commands.