1 /* ***********************************************************
2 * *
3 * Copyright, C Honeywell Information Systems Inc., 1984 *
4 * *
5 *********************************************************** */
6
7 cache_threshold_defaults_:
8 proc;
9
10 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
11 /* */
12 /* cache_threshold_defaults_ - this segment contains the default cache threshold values */
13 /* as defined by HIS LCPD HW Eng. as an acceptable error rate for the cache memory in */
14 /* the L68, DPS68 and DPS8 processors. */
15 /* */
16 /* Created: 2/84 by GA Texada */
17 /* */
18 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
19
20
21 /* format: style1,ind2,^inddcls,ifthenstmt,dclind2,declareind2,ifthendo,ifthen*/
22
23 dcl code fixed bin 35,
24 1 cdsa aligned like cds_args,
25 1 cache_threshold_defaults_ aligned like cache_threshold_data;
26
27 dcl addr null size string unspec builtin;
28
29 dcl com_err_ entry options variable,
30 create_data_segment_ entry ptr fixed bin 35;
31 ^L
32
33 unspec cache_threshold_defaults_ = ""b; /* start clean */
34 cache_threshold_defaults_.pri_dir_parity = 4; /* L68 use only */
35 cache_threshold_defaults_.port_buffer* = 1; /* HW Eng. said .2, but... */
36 cache_threshold_defaults_.pri_dir = 2;
37 cache_threshold_defaults_.wno_parity_any_port = 1;/* HW Eng. said .4 but... */
38 cache_threshold_defaults_.dup_dir_parity* = 1;
39 cache_threshold_defaults_.dup_dir_multimatch = 0; /* These are NOT acceptable */
40
41 cdsa.sections 1.p = addr cache_threshold_defaults_;
42 cdsa.sections 1.len = size cache_threshold_defaults_;
43 cdsa.sections 1.struct_name = "cache_threshold_defaults_";
44 cdsa.seg_name = "cache_threshold_defaults_";
45 cdsa.num_exclude_names = 0;
46 cdsa.exclude_array_ptr = null ;
47 string cdsa.switches = "0"b;
48 cdsa.switches.have_text = "1"b;
49 call create_data_segment_ addr cdsa code;
50 if code ^= 0 then call com_err_ code "cache_threshold_defaults_";
51 return;
52 ^L
53 %include cache_threshold_data;
54 ^L
55 %include cds_args;
56 end cache_threshold_defaults_;