1 /* ***********************************************************
  2    *                                                         *
  3    * Copyright, (C) Honeywell Information Systems Inc., 1982 *
  4    *                                                         *
  5    * Copyright (c) 1972 by Massachusetts Institute of        *
  6    * Technology and Honeywell Information Systems, Inc.      *
  7    *                                                         *
  8    *********************************************************** */
  9 
 10 hran_: proc;
 11 
 12           return;                                           /* do not enter here */
 13 
 14 /* hran_ - history register analyzer
 15    written by - E. J. Wallman Oct. 1974
 16    Modified by A. Downing March 1976 to add the set_stream entry for use in Multics HEALS.
 17    Also, all calls to ioa_ were changed to ioa_$ioa_switch, and calls to ioa_$nnl were changed
 18    to calls to ioa_$ioa_switch_nnl.
 19    Modified by RH Morrison in September, 1976 to squeeze the output format
 20    into 72 columns.  To do this, the octal printout of the history registers
 21    was eliminated from hran_$hranl since these registers are
 22    printed by cpu_reports_ prior to calling hranl.
 23    Modified by J. A. Bush in June 1977 to  allow for general use by heals_, ol_dump,
 24    and  mc_trace. The set_stream entry point was discarded in favor of a switch entry parameter.
 25    The long output conditional code was added to allow displaying of octal history  registers
 26    as well as symbolic data.
 27 
 28    Re-written in October 1980 by R. L. Coppola to accomodate analysis of
 29    registers for the DPS8 CPU which are different in structure and sometimes
 30    in length.  The DPS8 contains four sets (OU, DU/OU, and 2 APU) of registers
 31    each containing 64 double word history registers. However fim will only save
 32    the 16 MRU hregs in normal operation, BOS dumps will contain all 64.
 33 
 34    The analysis routines for the L68 and DPS8 have been placed in seperate
 35    external  sub-routines, this procedure will make a determination as to which
 36    analyzer is appropriate and then call it.
 37 */
 38 
 39 /*        This routine transposed from the original key of GMAP-flat
 40    to PL/I-sharp in October, 1974.  It decomposes the CP6100
 41    history register data saved in the prds and formats the data
 42    into easily readable lines in the order in which the various
 43    processor cycles occured.
 44 
 45    The routine has four entry points which are independent
 46    of each other. They are ...
 47 
 48    hrlgnd_l68_ Print a legend giving the definitions of all flags
 49                and symbols used in the output of the l68 analyzer.
 50 
 51 
 52    hrlgnd_dps8_ Print a legend giving the definitions of all flags
 53                 and symbols used in the output of the dps8 analyzer.
 54 
 55    hran_bos    Set the history register block size to 512 words
 56                instead of the normal 128 words.
 57 
 58    hranl_      Normal entry point for history register analysis.
 59                History register block size of 128 words default.
 60 
 61 
 62    display_      Normal entry point for display of history regs.
 63                  No attempt is made to "thread" them. The
 64                  interp_sw bit is used to enable interpretation
 65                  of the registers.
 66 
 67    All output goes to switch "output_switch". If a null iocb pointer
 68    is passed, then  the switch iox_$user_output is used as a default.
 69    Otherwise  "output_switch" is used as it is passed. If the long_output_sw = "0"b,
 70    then the octal contents of the history registers are not printed, therefore allowing
 71    the output to fit on an 80 character wide terminal. If the long_output_sw = "1"b,
 72    then the octal contents of the history registers is displayed as well as symbolic data.
 73 
 74 
 75    */
 76 
 77 /* ENTRIES */
 78 
 79 dcl  ioa_$ioa_switch options (variable),
 80      ioa_$ioa_switch_nnl entry options (variable),
 81      ioa_$rsnnl entry options (variable);
 82 dcl  hran_l68_$hranl_l68_ entry (ptr, ptr, bit (1));
 83 dcl  hran_dps8_$hranl_dps8_ entry (ptr, ptr, fixed bin, bit (1));
 84 dcl  hran_l68_$hranl_l68_bos entry (ptr, ptr, bit (1));
 85 dcl  hran_l68_$bos_no_thread entry (ptr, ptr, bit (5));
 86 dcl  hran_dps8_$no_thread entry (ptr, ptr, fixed bin, bit (5));
 87 dcl  hran_l68_$no_thread entry (ptr, ptr, bit (5));
 88 
 89 /* PARAMETERS */
 90 
 91 dcl (hr_data_ptr, a_iocbp) ptr;
 92 dcl  lo_sw bit (1);
 93 dcl  switches bit (5);                                      /* switches to display */
 94                                                             /* each hreg and how to display it */
 95                                                             /* must be in the following order */
 96                                                             /* expand_sw */
 97                                                             /* ou, cu, apu, du */
 98 
 99 /* AUTOMATIC STORAGE */
100 
101 
102 dcl  iocbp ptr,                                             /* output switch name */
103      iox_$user_output ptr ext,                              /* default io switch */
104      lo fixed;                                              /* long output sw, 1 => long output 2 => short output */
105 
106 dcl 1 apu_or_du_word aligned based (apu_or_duhrp),          /* first word of the apu or du regs */
107    (2 PAD bit (71),
108     2 apu_or_du_bit bit (1) unaligned);                     /* always on for a L68 CPU */
109 
110 dcl  ou_block1 bit (36 * 2 * 16) based;                     /* and the second */
111 dcl  (apu_or_duhrp, ouhrp) ptr;
112 dcl  nregs fixed bin;
113 dcl  threaded bit (1);
114 
115 /* OTHER */
116 
117 dcl  null builtin;
118 
119 %page;
120 hran_bos: entry (hr_data_ptr, a_iocbp, lo_sw);
121 
122           threaded = "1"b;
123           go to COMMON_BOS;
124 
125 bos_no_thread: entry  (hr_data_ptr, a_iocbp, switches);
126 
127 
128           threaded = "0"b;
129 
130 COMMON_BOS:
131 
132 /* Regs have been saved as a result of a crash (by BOS), need to determine
133    the type of CPU they are from */
134 
135                ouhrp = addrel (hr_data_ptr, 32);            /* set ptr to second block of ou data */
136                if ouhrp -> ou_block1 = "0"b then do;
137                                                             /* if empty these are from a l68 */
138 
139                   if threaded = "1"b then
140                   call hran_l68_$hranl_l68_bos (hr_data_ptr, a_iocbp, lo_sw);
141                                                             /* for now do same one */
142                   else call hran_l68_$bos_no_thread (hr_data_ptr, a_iocbp, switches);
143                   return;
144                   end;
145 
146                else do;                                     /* not empty, regs are from a dps8 */
147                     nregs = 64;                             /* 64 regs each are saved */
148                     if threaded = "1"b then
149                     call hran_dps8_$hranl_dps8_ (hr_data_ptr, a_iocbp, nregs, lo_sw);
150                     else call hran_dps8_$no_thread (hr_data_ptr, a_iocbp, nregs, switches);
151                     return;
152                end;
153 
154             return;
155 %page;
156 hranl:    entry (hr_data_ptr, a_iocbp, lo_sw);
157 
158           threaded = "1"b;
159           go to HRANL_COMMON;
160 
161 
162 no_thread:  entry (hr_data_ptr, a_iocbp, switches);
163 
164                    threaded = "0"b;
165 
166 HRANL_COMMON:
167 
168 /* regs were saved by fim but what type of CPU are they from */
169 
170 
171                nregs = 16;                                  /* we do know how many regs there are */
172                apu_or_duhrp = addrel (hr_data_ptr, 64);     /* set ptr to appropriate hreg block */
173 
174 /* Bit 71 of the L68 DU history registers is ALWAYS on, test it to determine CPU type */
175 
176                if apu_or_du_bit = "1"b then do;             /* it is a l68 */
177                   if threaded then
178                     call hran_l68_$hranl_l68_ (hr_data_ptr, a_iocbp, lo_sw) ;
179                     else call hran_l68_$no_thread (hr_data_ptr, a_iocbp, switches);
180                     return;
181                     end;
182 
183                else do;                                     /* no, its a dps8 */
184                   if threaded then
185                   call hran_dps8_$hranl_dps8_ (hr_data_ptr, a_iocbp, nregs, lo_sw);
186                   else call hran_dps8_$no_thread (hr_data_ptr, a_iocbp, nregs, switches);
187                   return;
188                   end;
189 
190           return;
191 
192 %page;
193 hrlgnd_dps8_: entry (a_iocbp);
194 
195 
196           if a_iocbp = null then                            /* called to use default switch */
197                iocbp = iox_$user_output;
198           else iocbp = a_iocbp;
199           call ioa_$ioa_switch (iocbp, "^|Abbreviations used in History Register Analysis for the DPS8 CPU^/^/");
200 
201           call ioa_$ioa_switch (iocbp, "^2/^12(_^)CU Legend^13(_^)^4x^12(_^)OU Legend^13(_^)");
202           call ioa_$ioa_switch (iocbp, "cy = cycle type (d = direct operand)^2x^1-   >>>flags<<<");
203           call ioa_$ioa_switch (iocbp, "(i=instr. fetch,o=operand,F=fault)^4xtrgo = transfer condition met");
204           call ioa_$ioa_switch (iocbp, "(n=indirect,x=xec,*=nop,e=EIS)^8xdl   = direct lower operand");
205           call ioa_$ioa_switch (iocbp, "mc = memory command^2-^8xdu   = direct upper operand");
206           call ioa_$ioa_switch (iocbp, "(00=rrs,sp; 04=rrs,dp; 10=rcl,sp)");
207           call ioa_$ioa_switch (iocbp, "(12=rmsk,sp; 16=rmsk,dp; 20=cwr,sp)");
208           call ioa_$ioa_switch (iocbp, "(24=cwr,dp; 32=smsk,sp; 36=smsk,dp)");
209           call ioa_$ioa_switch (iocbp, "(40=rd/lck; 54=rgr; 56=sgr)");
210           call ioa_$ioa_switch (iocbp, "(60=wrt/ulck; 62=con; 66=xec; 72=sxc)");
211           call ioa_$ioa_switch (iocbp, "^1->>>flags<<<");
212           call ioa_$ioa_switch (iocbp, "-y    = memory address invalid^8x<<<Indicator Register>>>");
213           call ioa_$ioa_switch (iocbp, "priv  = PRIV mode^2-^8xzero  = zero indicator");
214           call ioa_$ioa_switch (iocbp, "inf   = instruction fetch cycle^7xsign  = sign indicator");
215           call ioa_$ioa_switch (iocbp, "xint  = execute interrupt cycle^7xcarry = carry indicator");
216           call ioa_$ioa_switch (iocbp, "dir   = direct operand^1-^8xovfl  = overflow indicator");
217           call ioa_$ioa_switch (iocbp, "pfa   = prepare fault address^1-^8xeovfl = exponent overflow ");
218           call ioa_$ioa_switch (iocbp, "ic    = IC value is odd^1-^8xeufl  = exponent underflow");
219           call ioa_$ioa_switch (iocbp, "its   = AR/PR reference^1-^8xoflm  = overflow mask");
220           call ioa_$ioa_switch (iocbp, "inh   = inhibited instruction^1-^8xhex   = hex mode");
221           call ioa_$ioa_switch (iocbp, "poa   = prepare operand address");
222           call ioa_$ioa_switch (iocbp, "pai   = prepare interrupt address");
223           call ioa_$ioa_switch (iocbp, "pia   = prepare instruction address");
224           call ioa_$ioa_switch (iocbp, "pib   = port select logic busy");
225           call ioa_$ioa_switch (iocbp, "pon   = prepare operand next");
226           call ioa_$ioa_switch (iocbp, "pot   = prepare operand tally");
227           call ioa_$ioa_switch (iocbp, "raw   = request alter word");
228           call ioa_$ioa_switch (iocbp, "riw   = request indirect word");
229           call ioa_$ioa_switch (iocbp, "rpts  = executing repeat");
230           call ioa_$ioa_switch (iocbp, "saw   = store alter word");
231           call ioa_$ioa_switch (iocbp, "siw   = store indirect word");
232           call ioa_$ioa_switch (iocbp, "xde   = execute double from even ICT");
233           call ioa_$ioa_switch (iocbp, "xdo   = execute double from odd ICT");
234           call ioa_$ioa_switch (iocbp, "port  = memory cycle went to port");
235           call ioa_$ioa_switch (iocbp, "internal = memory cycle went to cache or direct");
236 
237           call ioa_$ioa_switch (iocbp, "^|^/^12(_^)DU Legend^13(_^)^4x^12(_^)APU Legend^12(_^)");
238           call ioa_$ioa_switch (iocbp, "mc     = data mode (b,4,6,9,w)^8xseg# = SDWAMR and PTWAMR numbers if");
239           call ioa_$ioa_switch (iocbp, "offset = descriptor counter^1-^8xcorresponding MATCH bits are set.");
240           call ioa_$ioa_switch (iocbp, "^1->>>flags<<<^1-^8xoffset = final store address");
241           call ioa_$ioa_switch (iocbp, "shftg = shift gate^11xmc = ring number (TSR.TRR)");
242           call ioa_$ioa_switch (iocbp, "d1a   = load alpha-num descriptor 1^13x>>>flags<<<");
243           call ioa_$ioa_switch (iocbp, "d2a   = load alpha-num descriptor 2^38tfanp      = final address, non-paged");
244           call ioa_$ioa_switch (iocbp, "anstr = alpha store^38tfap       = final address, paged");
245           call ioa_$ioa_switch (iocbp, "chrcy = character cycle^38tacv/dft   = access violation/directed fault");
246           call ioa_$ioa_switch (iocbp, "d1n   = load numeric descriptor 1^38tfdsptw    = fetch descriptor segment PTW");
247           call ioa_$ioa_switch (iocbp, "d2n   = load numeric descriptor 2^38tflthld    = acv/dft fault waiting");
248           call ioa_$ioa_switch (iocbp, "gstr  = decimal unit store^38tfsdw      = fetch SDW");
249           call ioa_$ioa_switch (iocbp, "lrw1  = load re-write reg 1 (1,2,3)^38tmdsptw    = modify descriptor segment PTW");
250           call ioa_$ioa_switch (iocbp, "lrw2  = load re-write reg 2^38tmptw      = modify PTW");
251           call ioa_$ioa_switch (iocbp, "ndsqf = end of sequence flag^38tfptw      = fetch PTW");
252           call ioa_$ioa_switch (iocbp, "dud   = decimal unit idle^38tfptw2     = fetch PTW+1 (for EIS Numerics)");
253           call ioa_$ioa_switch (iocbp, "duint = decimal unit interrupted^38tptwm      = MATCH in PTWAM");
254           call ioa_$ioa_switch (iocbp, "ndseq = end of sequence^38tsdwm      = MATCH in SDWAM");
255           call ioa_$ioa_switch (iocbp, "adcyc = add cycle^38tcache     = cache used for this cycle");
256           call ioa_$ioa_switch (iocbp, "sp3   = select pointer 3^38tpiapgbsy  = instruction fetch across");
257           call ioa_$ioa_switch (iocbp, "pop   = prepare operand pointer^50ta page boundary");
258           call ioa_$ioa_switch (iocbp, "sp1   = select pointer 1^38tpiaoosb   = instruction fetch went");
259           call ioa_$ioa_switch (iocbp, "sp2   = select pointer 2^50tout of segment bounds");
260           call ioa_$ioa_switch (iocbp, "lptr1 = Load Pointer #1^38tSDWAM-ERR = Multi-Match/Parity Error");
261           call ioa_$ioa_switch (iocbp, "lptr2 = Load Pointer #2^50tin SDW Assoc. Memory");
262           call ioa_$ioa_switch (iocbp, "addgC = add gate C^38tPTWAM-ERR = Multi-Match/Parity Error in");
263           call ioa_$ioa_switch (iocbp, "swseq = single word sequence^50tPTW Assoc. Memory");
264           call ioa_$ioa_switch (iocbp, "exh   = length exhaust");
265           call ioa_$ioa_switch (iocbp, "addgE = add gate E");
266           call ioa_$ioa_switch (iocbp, "addgF = add gate F");
267           call ioa_$ioa_switch (iocbp, "addgH = add gate H");
268           call ioa_$ioa_switch (iocbp, "btdgA = binary to decimal gate A");
269           call ioa_$ioa_switch (iocbp, "dfrst = processing descriptor for^/^8xthe first time.");
270 
271           return;
272 
273 %page;
274 
275 hrlgnd:   entry (a_iocbp);                                  /* for compatibility */
276 hrlgnd_l68_: entry (a_iocbp);
277 
278           if a_iocbp = null then                            /* called to use default switch */
279                iocbp = iox_$user_output;
280           else iocbp = a_iocbp;
281           call ioa_$ioa_switch (iocbp, "^|Abbreviations used in History Register Analysis for the L68 CPU^/^/");
282 
283           call ioa_$ioa_switch (iocbp, "^2/^12(_^)CU Legend^13(_^)^4x^12(_^)OU Legend^13(_^)");
284           call ioa_$ioa_switch (iocbp, "cy = cycle type (d = direct operand)^2x>>flags<<<");
285           call ioa_$ioa_switch (iocbp, "(i=instr. fetch,o=operand,F=fault)^4x9b = 9-bit byte (IT modifier only)");
286           call ioa_$ioa_switch (iocbp, "(n=indirect,x=xec,*=nop,e=EIS)^8xar = A-register in use");
287           call ioa_$ioa_switch (iocbp, "mc = memory command^2-^8xd1 = first divide cycle");
288           call ioa_$ioa_switch (iocbp, "(00=rrs,sp; 04=rrs,dp; 10=rcl,sp)^5xd2 = second divide cycle");
289           call ioa_$ioa_switch (iocbp, "(12=rmsk,sp; 16=rmsk,dp; 20=cwr,sp)^3xdl = direct lower operand");
290           call ioa_$ioa_switch (iocbp, "(24=cwr,dp; 32=smsk,sp; 36=smsk,dp)^3xdu = direct upper operand");
291           call ioa_$ioa_switch (iocbp, "(40=rd/lck; 54=rgr; 56=sgr)^1-^8xin = first ou cycle");
292           call ioa_$ioa_switch (iocbp, "(60=wrt/ulck; 62=con; 66=xec; 72=sxc)^1xit = IT character modifier");
293           call ioa_$ioa_switch (iocbp, ">>>flags<<<^2-^8xoa = mantissa alignment cycle");
294           call ioa_$ioa_switch (iocbp, "-y = memory address invalid^1-^8xoe = exponent compare cycle");
295           call ioa_$ioa_switch (iocbp, "br = BAR mode^2-^8xof = final OU cycle");
296           call ioa_$ioa_switch (iocbp, "cl = control unit load^1-^8xom = general OU cycle");
297           call ioa_$ioa_switch (iocbp, "cs = control unit store^1-^8xon = normalize cycle");
298           call ioa_$ioa_switch (iocbp, "dr = direct operand^2-^8xos = second cycle of multiple ops");
299           call ioa_$ioa_switch (iocbp, "fa = prepare fault address^1-^8xqr = Q-register in use");
300           call ioa_$ioa_switch (iocbp, "ic = IC value is odd^1-^8xrb = opcode buffer loaded");
301           call ioa_$ioa_switch (iocbp, "it = AR/PR reference^1-^8xrp = primary register loaded");
302           call ioa_$ioa_switch (iocbp, "in = inhibited instruction^1-^8xrs = secondary register loaded");
303           call ioa_$ioa_switch (iocbp, "ol = operations unit load^1-^8xsd = store data available");
304           call ioa_$ioa_switch (iocbp, "os = operations unit store^1-^8x-d = data not available");
305           call ioa_$ioa_switch (iocbp, "pa = prepare operand address^1-^8xx0 = index 0 in use");
306           call ioa_$ioa_switch (iocbp, "pb = port busy _^Ho_^Hr data from cache^5xx1 = index 1 in use");
307           call ioa_$ioa_switch (iocbp, "pi = prepare instruction address^6xx2 = index 2 in use");
308           call ioa_$ioa_switch (iocbp, "pl = port select logic not busy^7xx3 = index 3 in use");
309           call ioa_$ioa_switch (iocbp, "pn = prepare final indirect address^3xx4 = index 4 in use");
310           call ioa_$ioa_switch (iocbp, "pt = prepare operand tally^1-^8xx5 = index 5 in use");
311           call ioa_$ioa_switch (iocbp, "ra = request alter word^1-^8xx6 = index 6 in use");
312           call ioa_$ioa_switch (iocbp, "ri = request indirect word^1-^8xx7 = index 7 in use");
313           call ioa_$ioa_switch (iocbp, "rp = executing repeat");
314           call ioa_$ioa_switch (iocbp, "sa = store alter word");
315           call ioa_$ioa_switch (iocbp, "si = store indirect word");
316           call ioa_$ioa_switch (iocbp, "tr = transfer condition met");
317           call ioa_$ioa_switch (iocbp, "wi = request instruction fetch");
318           call ioa_$ioa_switch (iocbp, "xa = prepare execute interrupt address");
319           call ioa_$ioa_switch (iocbp, "xe = execute double from even ICT");
320           call ioa_$ioa_switch (iocbp, "xi = execute interrupt present");
321           call ioa_$ioa_switch (iocbp, "xo = execute double from odd ICT");
322 
323           call ioa_$ioa_switch (iocbp, "^|^/^12(_^)DU Legend^13(_^)^4x^12(_^)APU Legend^12(_^)");
324           call ioa_$ioa_switch (iocbp, "mc = data mode (b,4,6,9,w)^1-^8xseg# = SDWAMR and PTWAMR numbers if");
325           call ioa_$ioa_switch (iocbp, "offset = descriptor counter^1-^8xcorresponding MATCH bits are set.");
326           call ioa_$ioa_switch (iocbp, ">>>flags<<<^2-^8xoffset = final store address");
327           call ioa_$ioa_switch (iocbp, "()a = prepare alignment count for^5xmc = ring number (TSR.TRR)");
328           call ioa_$ioa_switch (iocbp, "^6xnumeric operand (1,2)");
329           call ioa_$ioa_switch (iocbp, "a() = load alpha operand (1,2)^8x>>>flags<<<");
330           call ioa_$ioa_switch (iocbp, "al = adjust length^2-^8xan = final address, non-paged");
331           call ioa_$ioa_switch (iocbp, "as = alpha store^2-^8xap = final address, paged");
332           call ioa_$ioa_switch (iocbp, "bd = binary-decimal execution^1-^8xf  = access violation or directed fault");
333           call ioa_$ioa_switch (iocbp, "bg = blanking gate^2-^8xfd = fetch descriptor segment PTW");
334           call ioa_$ioa_switch (iocbp, "c0 = force stc0^2-^8xfh = fault waiting");
335           call ioa_$ioa_switch (iocbp, "cg = character operation^1-^8xfs = fetch SDW");
336           call ioa_$ioa_switch (iocbp, "d() = descriptor active (1,2,3)^7xmd = modify descriptor segment PTW");
337           call ioa_$ioa_switch (iocbp, "da = data available^2-^8xmp = modify PTW");
338           call ioa_$ioa_switch (iocbp, "db = decimal-binary execution^1-^8xp1 = fetch PTW");
339           call ioa_$ioa_switch (iocbp, "dd = decimal unit idle^1-^8xp2 = fetch PTW+1");
340           call ioa_$ioa_switch (iocbp, "di = decimal unit interrupted^1-^8xpm = MATCH in PTWAM");
341           call ioa_$ioa_switch (iocbp, "dl = decimal unit load^1-^8xsm = MATCH in SDWAM");
342           call ioa_$ioa_switch (iocbp, "ds = decimal unit store");
343           call ioa_$ioa_switch (iocbp, "ei = mid-instruction interrupt enabled");
344           call ioa_$ioa_switch (iocbp, "en = end instruction");
345           call ioa_$ioa_switch (iocbp, "es = end sequence");
346           call ioa_$ioa_switch (iocbp, "ff = floating result");
347           call ioa_$ioa_switch (iocbp, "fl = first data buffer load");
348           call ioa_$ioa_switch (iocbp, "fp = first pointer preparation");
349           call ioa_$ioa_switch (iocbp, "fs = end sequence");
350           call ioa_$ioa_switch (iocbp, "l() = load descriptor (1,2,3)");
351           call ioa_$ioa_switch (iocbp, "ld = length = direct");
352           call ioa_$ioa_switch (iocbp, "lf = end first pointer preparation");
353           call ioa_$ioa_switch (iocbp, "lv = level < word size");
354           call ioa_$ioa_switch (iocbp, "lx = length exhaust");
355           call ioa_$ioa_switch (iocbp, "l< = length < 128");
356           call ioa_$ioa_switch (iocbp, "mp = executing MOPs");
357           call ioa_$ioa_switch (iocbp, "n() = load numeric operand (1,2)");
358           call ioa_$ioa_switch (iocbp, "nd = need descriptor");
359           call ioa_$ioa_switch (iocbp, "ns = numeric store");
360           call ioa_$ioa_switch (iocbp, "op = operand available");
361           call ioa_$ioa_switch (iocbp, "pc = alpha packing cycle");
362           call ioa_$ioa_switch (iocbp, "pl = prepare operand length");
363           call ioa_$ioa_switch (iocbp, "pp = prepare operand pointer");
364           call ioa_$ioa_switch (iocbp, "r() = load rewrite register (1,2)");
365           call ioa_$ioa_switch (iocbp, "re = write-back partial word");
366           call ioa_$ioa_switch (iocbp, "rf = rounding");
367           call ioa_$ioa_switch (iocbp, "rl = rewrite register 1 loaded");
368           call ioa_$ioa_switch (iocbp, "rw = du=rd+wt control interlock");
369           call ioa_$ioa_switch (iocbp, "sa = select address register");
370           call ioa_$ioa_switch (iocbp, "sg = shift procedure");
371           call ioa_$ioa_switch (iocbp, "xg = exponent network");
372           call ioa_$ioa_switch (iocbp, "xm = extended al,ql modifier");
373           call ioa_$ioa_switch (iocbp, "+g = add-subtract execution");
374           call ioa_$ioa_switch (iocbp, "*g = multiply-divide execution");
375 
376           return;
377 
378      end hran_;