1 /* ***********************************************************
2 * *
3 * Copyright, C Honeywell Bull Inc., 1987 *
4 * *
5 * Copyright, C Honeywell Information Systems Inc., 1982 *
6 * *
7 *********************************************************** */
8
9 /* PRDS - The Processor Data Segment and Processor Stack.
10 /* Last modified Date and reason:
11 2/6/76 by S. Webber Initial coding
12 6/15/77 by M. Weaver to null signal and sct pointers
13 8/25/80 by J. A. Bush for the dps8/70m cpu
14 2/22/81 by J. Bongiovanni for fast_connect_code
15 6/27/81 by J. Bongiovanni for idle_temp
16 10/11/83 by R. Coppola to adjust for size change of fast connect code
17 and validate that apt_ptr& ignore_pl are on correct mod
18 */
19
20
21 /* HISTORY COMMENTS:
22 1) change88-05-24Farley, approve88-06-30MCR7927,
23 audit88-07-12Fawcett, install88-08-02MR12.2-1076:
24 Added fault_reg_last_saved and hregs_last_saved time values, to make sure
25 that the associated data is only saved once per fault.
26 END HISTORY COMMENTS */
27
28
29 /* ******************************************************
30 * *
31 * *
32 * Copyright c 1972 by Massachusetts Institute of *
33 * Technology and Honeywell Information Systems, Inc. *
34 * *
35 * *
36 ****************************************************** */
37
38
39 prds: proc;
40
41 /* This program creates the prds data base */
42
43 /* Automatic */
44
45 dcl 1 cdsa aligned like cds_args;
46 dcl code fixed bin 35;
47
48 /* Static */
49
50 dcl prdsname char 4 aligned static init "prds" options constant;
51 dcl exclude_pad 1 char 32 aligned static options constant init "pad*";
52
53 /* The following must correspond to the size of the fast connect code in
54 fast_connect_init */
55
56 dcl FAST_CONNECT_CODE_WORDS init 72 fixed bin int static options constant;
57
58 /* Builtins */
59
60 dcl addr bin mod rel size string unspec builtin;
61
62 /* Entries */
63
64 dcl com_err_ entry options variable;
65 dcl create_data_segment_ entry ptr fixed bin 35;
66 dcl get_temp_segment_ entry char * ptr fixed bin 35;
67 dcl release_temp_segment_ entry char * ptr fixed bin 35;
68
69
70 ^L
71
72 dcl prdsp ptr;
73
74 dcl 1 prds aligned based prdsp,
75 2 header aligned like stack_header, /* standard stack header */
76 2 interrupt_data aligned like mc, /* MC for interrupts */
77 2 fim_data aligned like mc, /* MC for connect faults, timer runouts */
78 2 sys_trouble_data aligned like mc, /* MC for saved sys trouble data */
79 2 ignore_data aligned like scu, /* for SCU data to be ignored at certain times */
80 2 iitemp fixed bin 71, /* temporary used by ii surprise! */
81 2 last_recorded_time fixed bin 71, /* used by traffic control */
82 2 idle_ptr ptr, /* pointer to idle process APTE for this processor */
83 2 simulated_mask fixed bin 71, /* simulated system controller mask register */
84 2 am_data bit 0, /* to get addr of associative memory data block */
85 2 ptw_am_regs 4*16 fixed bin 35, /* page table regs 4 sets of 16 for dps8/70m */
86 2 ptw_am_ptrs 4*16 fixed bin 35, /* page table pointers 4 sets of 16 for dps8/70m */
87 2 sdw_am_regs 4*16 fixed bin 71, /* segment desc. regs 4 sets of 16 for dps8/70m */
88 2 sdw_am_ptrs 4*16 fixed bin 35, /* segment desc. pointers 4 sets of 16 for dps8/70m */
89 2 processor_pattern bit 8 aligned, /* 1 bit ON for this processor */
90 2 processor_tag fixed bin 3, /* CPU tag from maintenance panel */
91 2 last_timer_setting bit 27 aligned, /* last timer value loaded for this CPU */
92 2 depth fixed bin, /* depth in eligible queue for running process */
93 2 mode_reg bit 36 aligned, /* mode register for this processor */
94 2 cache_luf_reg bit 36 aligned, /* cache mode register for this CPU */
95 2 fault_reg bit 72 aligned, /* place to store the fault register */
96 2 fault_reg_last_saved fixed bin 71, /* time register last saved */
97 2 hregs_last_saved fixed bin 71, /* time history regs last saved */
98 2 apt_ptr ptr, /* -> apte running on this cpu */
99 2 idle_temp fixed bin 71, /* used by idle process */
100
101
102 /* The following contains code used for handling connect faults for this processor */
103
104
105 2 fast_connect_code FAST_CONNECT_CODE_WORDS bit 36 aligned,
106 2 fast_connect_code_end bit 36 aligned, /* marker for fast_connect_init */
107 2 mode_reg_enabled bit 36 aligned, /* used to set mode register */
108 2 pad_mod_8 6 fixed bin,
109 2 ignore_pl 8 bit 36 aligned, /* used by wired fim to spl/lpl */
110 2 pad_mod_16 8 bit 36 aligned,
111 2 processor_stack aligned like stack_frame; /* first stack frame location */
112
113 ^L
114
115 call get_temp_segment_ "prds" prdsp code;
116
117 unspec prds = ""b;
118
119
120 /* Now make some checks on alignment of certain variables */
121
122 call check addr prds.idle_ptr "idle_ptr" 2;
123 call check addr prds.processor_stack "processor_stack" 16;
124 call check addr prds.ptw_am_regs "ptw_am_regs" 16;
125 call check addr prds.sdw_am_regs "sdw_am_regs" 32;
126 call check addr prds.fast_connect_code "fast_connect_code" 2;
127 call check addr prds.ignore_pl "ignore_pl"8;
128 call check addr prds.apt_ptr "apt_ptr" 2;
129
130 /* Now set up call to create data base */
131
132 cdsa.sections 1.p = addr prds;
133 cdsa.sections 1.len = size prds;
134 cdsa.sections 1.struct_name = "prds";
135
136 cdsa.seg_name = "prds";
137 cdsa.num_exclude_names = 1;
138 cdsa.exclude_array_ptr = addr exclude_pad;
139
140 string cdsa.switches = "0"b;
141 cdsa.switches.have_text = "1"b;
142
143 call create_data_segment_ addr cdsa code;
144
145 call release_temp_segment_ "prds" prdsp code;
146
147 ^L
148
149 check: proc where message modulo;
150
151 dcl where ptr;
152 dcl message char *;
153 dcl modulo fixed bin;
154
155 if mod bin rel where 18 modulo ^= 0
156 then call com_err_ 0 prdsname "The variable ^a is not aligned on a ^d-word boundary." message modulo;
157
158 end check;
159
160 ^L
161 % include cds_args;
162
163 ^L
164 % include stack_header;
165
166 ^L
167 % include stack_frame;
168
169 % include mc;
170
171
172 end prds;