1 " ***********************************************************
2 " * *
3 " * Copyright, C Honeywell Bull Inc., 1987 *
4 " * *
5 " * Copyright, C Honeywell Information Systems Inc., 1982 *
6 " * *
7 " * Copyright c 1972 by Massachusetts Institute of *
8 " * Technology and Honeywell Information Systems, Inc. *
9 " * *
10 " ***********************************************************
11 entry init,start_bootload_cpu,return
12
13 segdef wait_flag flag cleared by new processor
14 segdef controller_data bits for online controllers
15 segdef new_dbr DBR for new processor
16 segdef first_tra TRA instruction to start new processor
17 segdef trouble_tra TRA instruction if trouble starting
18 segdef startup_tra TRA instruction if startup fault
19 segdef lockup_tra TRA instruction if lockup fault
20 segdef onc_tra TRA instruction if op-not-complete fault
21
22
23 "^L
24
25 include mode_reg
26
27 include cache_mode_reg
28
29 "^L
30
31 " INIT - Initialization Entry.
32
33 init:
34 absa first_steps get absolute address
35 als 6 in AU
36 orsa first_tra and set TRA instruction
37
38 absa trouble_start get absolute address
39 als 6 in AU
40 orsa trouble_tra set for bad startup
41
42 absa startup_start get absolute address
43 als 6 in AU
44 orsa startup_tra set for bad startup
45
46 absa lockup_start get absolute address
47 als 6 in AU
48 orsa lockup_tra set for bad lockup
49
50 absa onc_start get absolute address
51 als 6 in AU
52 orsa onc_tra set for bad onc
53
54 absa cache_off get absolute address of cache off template
55 als 6 in AU
56 orsa set_cache_off set in y field of cache off lcpr
57
58 absa scs$processor_switch_data
59 als 6 get absolute address
60 sta switch_data save for checking switches
61
62 absa scs$processor_switch_template
63 als 6 get absolute address
64 sta switch_test save for checking switches
65
66 absa scs$processor_switch_compare
67 als 6 get absolute address
68 sta switch_discrep save for checking switches
69
70 absa scs$processor_switch_mask
71 als 6 get absolute address
72 sta switch_and save for checking switches
73
74 eppbp second_step bp -> place to enter appending mode
75 spribp continue save for use by new processor
76
77 short_return
78
79
80 " ^L
81
82 " START_BOOTLOAD_CPU - Entry to Start Idle Process for Bootload CPU.
83
84 start_bootload_cpu:
85 push
86 spri prs save prs for new CPU
87 sprisp pds$last_sp make sure we get sp set correctly
88 "
89 ldbr new_dbr load new DBR for idle process
90 tra second_step and go to idle process initialization
91
92
93
94 " tc_init has fixed things with pxss so that we will continue running
95 " at the following instruction.
96 "
97 return:
98 return
99
100
101 " ^L
102 " The first steps of the initialized processor ...
103 "
104 " The processor reaches this point still in absolute mode. The
105 " DBR must be loaded, and then appending mode ...
106
107 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+>
108 first_steps:
109 sti indic-*,ic save indicators
110 lda indic-*,ic pick up indicators
111 cana scu.ir.abs,dl in abs mode?
112 tze gcoserr-*,ic if not, CPU is in wrong mode
113 set_cache_off:
114 lcpr 0,02 turn cache off before we get into trouble.
115 eax3 0
116 eax7 0 read processor switches
117 ldx6 switch_test-*,ic this code executes in ABSOLUTE MODE
118 ldx5 switch_discrep-*,ic ..
119 ldx4 switch_data-*,ic ..
120 swtest1: rsw 0,7 read processor switches
121 sta 0,4 and save
122 era 0,6 generate discrepancy data
123 sta 0,5 and store
124 eax5 1,5 ..
125 eax6 1,6 ..
126 cmpx7 2,du was this an rsw 2?
127 tnz swtest2-*,ic xfer if no
128 lda 0,4 yes, load rsw 2 data
129 lrl 30 position cpu type in AL
130 ana 3,dl and out all but cpu type
131 tze swtest2-*,ic xfer if L68 or DPS cpu
132 eax3 0,al copy cpu type into x3
133 tra swtest3-*,ic and go check switches
134
135 swtest2: cmpx7 4,du was last instuction rsw 4?
136 tze swtest3-*,ic yes, go check switches
137 eax4 1,4 increment rsw data storage
138 eax7 1,7 loop until finished
139 tra swtest1-*,ic ..
140
141 swtest3: eax7 0 see if any switches are set wrongly
142 ldx6 switch_discrep-*,ic remember, ABSOLUTE MODE
143 ldx5 switch_and-*,ic ..
144 swtest4: lda 0,6 pick up discrepancy data
145 cana 0,5 any bits on?
146 tnz swerr-*,ic if so, stop now
147 eax5 1,5 check all switches
148 eax6 1,6 ..
149 cmpx7 2,du was this data from an rsw 2?
150 tnz swtest5-*,ic xfer if no
151 cmpx3 1,du yes, is this a DPS8 CPU?
152 tze swtest6-*,ic xfer if yes
153 swtest5: cmpx7 4,du is this data from an rsw 4?
154 tze swtest6-*,ic yes, we are all done
155 eax7 1,7 ..
156 tra swtest4-*,ic ..
157
158 swerr: lda rcerr_addcpu_bad_switches,dl
159 sta wait_flag-*,ic set it for start_cpu
160 swerr_lp: ldt =o77777,du prevent timer runout faults
161 lda wait_flag-*,ic has start_cpu given use a green lite?
162 tmi nogo-*,ic no, bad switches go to DIS
163 cmpa rcerr_addcpu_bad_switches,dl is start_cpu still thinking about it?
164 tze swerr_lp-*,ic yes, go through another loop
165
166 swtest6:
167 eax7 0 controller port number in X7
168 ctest1: lda controller_data-*,ic get controllers online
169 tpl 2,ic if this one offline, skip reference
170 rccl 0,7 if controller port not enabled, get onc fault
171 nop 0,du allow possible onc to "take"
172 nop 0,du ..
173 eax7 32768,7 step to next port
174 lda controller_data-*,ic get controllers online
175 als 1 shift to next controller
176 sta controller_data-*,ic replace data
177 tnz ctest1-*,ic loop if more to do
178
179 scu cudata-*,ic store control unit
180 lda scu.apu.pt_on+scu.apu.sd_on,dl AM's on?
181 cnaa cudata-*+scu.apu_stat_word,ic
182 tnz amerr-*,ic if not, stop
183
184 ldbr new_dbr-*,ic load the DBR
185 tra continue-*,ic* enter appending mode
186
187 " ^L
188
189 trouble_start:
190 lda rcerr_addcpu_trouble,dl
191 tra nogo-*,ic
192
193 startup_start:
194 lda rcerr_addcpu_startup,dl
195 tra nogo-*,ic
196
197 lockup_start:
198 lda rcerr_addcpu_lockup,dl
199 tra nogo-*,ic
200
201 amerr: lda rcerr_addcpu_amoff,dl
202 tra nogo-*,ic
203
204 onc_start:
205 eaa 0,7 port number in A
206 arl 33
207 ldx7 switch_discrep-*,ic store for error analysis
208 sta -3,7 ..
209 lda rcerr_addcpu_enable,dl
210 tra nogo-*,ic
211
212 gcoserr: lda rcerr_addcpu_gcos,dl tried to add CPU in GCOS mode
213
214 nogo: sta wait_flag-*,ic
215 dis -1
216 tra -1,ic
217
218 " ^L
219
220 bool hist_on,mr.enable_mr+mr.enable_hist
221 bool cache_on,cmr.cache_1_on+cmr.cache_2_on+cmr.operands_from_cache+cmr.inst_from_cache
222
223 "
224 " All checks have been passed--start running
225 "
226
227 second_step:
228 lpri prs load the pointer registers with good stuff
229
230 ldt 1,du set initial value
231 stt prds$last_timer_setting
232
233 eax6 0 initialize cache size to 0 no cache
234 rsw 2 get cpu type in a reg
235 eax7 64 64 hregs on DPS8 CPU
236 cana =o10000,du is it a DPS8 cpu?
237 tnz cpu_dps8 xfer if yes
238 eax7 16 only 16 hregs for L68 or DPS cpus
239 cana =o400,dl L68 with cache?
240 tze init_hregs No, L68 with no cache
241 eax6 1 yes, set cache size for 2K
242 tra init_hregs
243
244 cpu_dps8:
245 epplb reg_storage get ptr to store funny CMR
246 scpr lb|2,06 Note, must have addr bit 16 on
247 lda lb|3 load cache size word
248 ana =o3400,dl and out all but size
249 tnz ck_vs_sc is it old style 8K?
250 eax6 2 yes, set index
251 tra init_hregs
252
253 ck_vs_sc: eax6 5 start with 32K size
254 als 24 bit 60 to A0
255 c_sz_lp: als 1 position indicator bit
256 tmoz init_hregs exit if we got a hit
257 eax6 -1,6 decrement cache size
258 tra c_sz_lp
259 init_hregs:
260 lcpr 0,03 reset history reg
261 eax7 -1,7
262 tpnz init_hregs
263
264 lxl1 prds$processor_tag get our CPU tag
265 lda =o77,dl
266 ansa scs$processor_data,1 reset all bits but port number
267 orsx6 scs$processor_data,1 store cache size
268 xec cache_ctr_tab,1 LB => wired_hardcore_data cache err ctrs
269 sxl6 lb|0 save cache size&type there also
270 epplb prds$cache_luf_reg get setting for lockup/cache control
271 lda cache_on+3,dl set lockup fault reg
272 sta lb|0 set bits to allow cache to run
273
274 "************************************* Cache is enabled for first time here****************
275
276 lcpr lb|0,02 load luf/cache register
277 cams 4 clear cache on L68 and DPS no effect on DPS8
278
279 scpr indic,01 store and clear the fault register
280
281 lda prds$mode_reg start history regs and start cache
282 ora hist_on,dl enable history regs, stop for fault
283 sta prds$mode_reg_enabled
284 epplb prds$mode_reg_enabled
285 lcpr lb|0,04 load mode reg
286
287 eppbp prds$idle_ptr,* apte for idle process this cpu
288 spribp prds$apt_ptr mark as apte for running process this cpu
289 ldx0 running,du we must tell traffic controller
290 sxl0 bp|apte.state that state is running
291
292 rccl sys_info$clock_,* read the calendar clock
293 staq pds$cpu_time initialize cause pxss won't
294 staq prds$last_recorded_time initialize this, too.
295
296 " Now that the processor is fully initialized, reflect this in the SCS.
297
298 lda processor_data.online+processor_data.interrupt_cpu,du
299 orsa scs$processor_data,1
300 lda =o400000,du turn on high-order bit
301 arl 0,1 shift to correct position
302 sta prds$processor_pattern set correct bit
303 orsa scs$processor indicate CPU now running
304
305 " ^L
306
307 " Clear flag that start_cpu is waiting on. Then, wait
308 " for start_cpu to undo the connect lock.
309
310 stz wait_flag signal that we are running
311
312 szn scs$connect_lock connect lock cleared?
313 tze *+4 if so, exit loop
314 llr 72 wait for a while
315 llr 72 ..
316 tra *-4 ..
317
318 eppsp =its-11,* null pointer for sp in idle processors
319
320
321 " Send a connect to pre-empt the idle process.
322 " Then open the mask to allow interrupts.
323
324 ldq apte.pre_empt_pending,du pre_empt the processor
325 orsq bp|apte.flags
326 cioc scs$cow_ptrs,1*
327
328 ldaq scs$open_level open up the mask
329 xec scs$set_mask,1
330
331 " ^L
332
333 "
334 " Idle with a flashing pattern in the lights.
335 "
336 " This is a convenient place to recompute tc_data$max_timer_register,
337 " which is the product of the number of CPUs and the tuning parameter
338 " tc_data$pre_empt_sample time. Either of these values may have
339 " changed due to reconfiguration or tuning parameter changes, and
340 " we don't have much else to do here, so ...
341
342 ldaq flash_pattern
343
344 inhibit off <-><-><-><-><-><-><-><-><-><-><-><->
345 idle_dis: dis 0
346 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+>
347
348 " The following code checks to see if a connect has been delayed.
349 " This is done by seeing if the ring alarm register is nonzero.
350 " If it is, the connect must be reissued now.
351
352 sznc pds$alarm_ring is ring alarm set?
353 tze *+2 if not, skip connect reissue
354 cioc scs$cow_ptrs,1*
355
356 staq prds$idle_temp save flash pattern
357 ldq tc_data$pre_empt_sample_time
358 mpy tc_data$ncpu
359 tze reload_flash bogus for some reason
360 staq tc_data$max_timer_register
361
362 reload_flash:
363 ldaq prds$idle_temp
364 alr 35
365 qlr 1
366
367 eax7 0,au flash pattern in X7
368 lxl4 tc_data$n_eligible # of eligible processes in X4
369 ldx5 bp|apte.term_processid idle type in X5
370 lxl6 tc_data$stat+2 # of ready processes in X6
371
372 tra idle_dis
373
374 inhibit off <-><-><-><-><-><-><-><-><-><-><-><->
375
376 "^L
377 mod 16
378 prs: bss ,16
379
380 cudata: bss ,8
381
382 new_dbr: bss ,2
383
384 cache_off:
385 oct 3 template for turning cache off
386 even
387 flash_pattern:
388 zero -1,0
389 zero 0,-1
390
391 continue:
392 its -1,1
393
394 reg_storage:
395 bss ,4
396
397 switch_data:
398 arg 0
399
400 switch_test:
401 arg 0
402
403 switch_and:
404 arg 0
405
406 switch_discrep:
407 arg 0
408
409 controller_data:
410 vfd 8/0
411
412 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+>
413 first_tra:
414 tra 0
415 trouble_tra:
416 tra 0
417 startup_tra:
418 tra 0
419 lockup_tra:
420 tra 0
421 onc_tra:
422 tra 0
423 inhibit off <-><-><-><-><-><-><-><-><-><-><-><->
424
425 even
426 indic: bss ,2
427
428 wait_flag:
429 oct 0
430 inhibit on
431 cache_ctr_tab:
432 epplb wired_hardcore_data$cpu_a_cache_err_ctr_array
433 epplb wired_hardcore_data$cpu_b_cache_err_ctr_array
434 epplb wired_hardcore_data$cpu_c_cache_err_ctr_array
435 epplb wired_hardcore_data$cpu_d_cache_err_ctr_array
436 epplb wired_hardcore_data$cpu_e_cache_err_ctr_array
437 epplb wired_hardcore_data$cpu_f_cache_err_ctr_array
438 epplb wired_hardcore_data$cpu_g_cache_err_ctr_array
439 epplb wired_hardcore_data$cpu_h_cache_err_ctr_array
440 inhibit off
441 "^L
442 include scs
443
444 include rcerr
445
446 include mc
447
448 " ^L
449 include state_equs
450
451 include apte
452
453
454 end