1 /****^  ***********************************************************
  2         *                                                         *
  3         * Copyright, (C) Honeywell Bull Inc., 1987                *
  4         *                                                         *
  5         * Copyright, (C) Honeywell Information Systems Inc., 1982 *
  6         *                                                         *
  7         *********************************************************** */
  8 /* SCR_UTIL - Procedure to Manipulate System Controller Registers and Data.
  9    coded 2/1/76 by Noel I. Morris
 10    modified 5/11/78 by J. A. Bush for processor testing
 11    modified 2/5/79 by B. Greenberg for port expanders.
 12    modified May 1981 by J. Bongiovanni to set anti-hog switches,
 13         validate sscr
 14 */
 15 
 16 
 17 /* ******************************************************
 18    *                                                    *
 19    *                                                    *
 20    * Copyright (c) 1972 by Massachusetts Institute of   *
 21    * Technology and Honeywell Information Systems, Inc. *
 22    *                                                    *
 23    *                                                    *
 24    ****************************************************** */
 25 
 26 
 27 scr_util$read_cfg: proc (port);
 28 
 29 dcl  port fixed bin (3);                                    /* controller port number on active modules */
 30 
 31 dcl  mr_data fixed bin (71),                                /* data from RSCR-MR */
 32      i fixed bin,                                           /* iteration variable */
 33      ctag fixed bin (3),                                    /* system controller tag */
 34      bitno fixed bin,                                       /* mask bit offset */
 35      iscu fixed bin (5),                                    /* ISOLTS SCU tag */
 36      icpu fixed bin (5),                                    /* ISOLTS CPU tag */
 37      mcpu fixed bin (5),                                    /* ISOLTS mask cpu */
 38     (maska, maskb) bit (9),                                 /* temporary mask reg storage */
 39     (store_a_size, store_b_size) fixed bin (17),            /* size of stores A & B */
 40     scr_cfg2_temp fixed bin (71) aligned,                   /* temp rscr storage                              */
 41     set_cfg_try_count fixed bin,                            /* number times tried sscr                        */
 42     set_cfg_ok bit (1) aligned,
 43     mask_a_val char (3),
 44     mask_b_val char (3),
 45     cycle_priority_bits (7) bit (1),
 46     port_enable_bits (8) bit (1),
 47     nea_bits (7) bit (1);
 48 
 49 
 50 
 51 
 52 dcl 1 cdata aligned like scs$controller_data based (cdp),   /* single element of scs$controller data */
 53      cdp ptr,                                               /* pointer to the above */
 54     1 pdata aligned like scs$processor_data based (pdp),    /* single element of scs$processor_data */
 55      pdp ptr;                                               /* pointer to the above */
 56 
 57 dcl  masks (3) bit (72) aligned based (mkp),                /* array of interrupt masks */
 58      mkp ptr;                                               /* pointer to the above */
 59 
 60 dcl  scr_cfg2_temp_overlay bit (72) aligned defined (scr_cfg2_temp);
 61 
 62 
 63 dcl  SCR_CFG2_PROGRAM_MASK bit (72) aligned int static options (constant)
 64         init ("777774037777777000077417"b3);                /* program settable bits in config register       */
 65 dcl  SET_CFG_TRY_LIMIT fixed bin int static options (constant)
 66         init (10);                                          /* number sscr attempts before punting            */
 67 dcl  LETTERS char (8) int static options (constant) init ("ABCDEFGH");
 68 
 69 dcl  privileged_mode_ut$cioc entry (ptr),
 70      privileged_mode_ut$rscr entry (fixed bin (3), fixed bin (6), fixed bin (71)),
 71      privileged_mode_ut$sscr entry (fixed bin (3), fixed bin (6), fixed bin (71)),
 72      privileged_mode_ut$smcm entry (fixed bin (3), bit (72) aligned),
 73      syserr entry options (variable);
 74 
 75 
 76 dcl (addr, bin, bit, convert, index, mod, string, substr, unspec) builtin;
 77 
 78 ^L
 79 
 80 % include scs;
 81 
 82 ^L
 83 % include scr;
 84 
 85 ^L
 86 
 87           cdp = addr (scs$controller_data (port));          /* Get pointer to appropriate element of array. */
 88 
 89           call privileged_mode_ut$rscr (port, SC_MR, mr_data); /* Read the controller mode register. */
 90           scrp = addr (mr_data);                            /* Set pointer to data read. */
 91           cdata.type = scr_mr.identification;               /* Extract the controller ID code. */
 92 
 93           call privileged_mode_ut$rscr (port, SC_CFG, scs$cfg_data (port));
 94           scrp = addr (scs$cfg_data (port));                /* Read configuration data from controller. */
 95 
 96           if cdata.type >= "0010"b then do;                 /* If 4MW SCU ... */
 97                cdata.store_a_online = scr_cfg2.a_online;
 98                cdata.store_a1_online = scr_cfg2.a1_online;
 99                cdata.store_b_online = scr_cfg2.b_online;
100                cdata.store_b1_online = scr_cfg2.b1_online;
101                cdata.store_b_is_lower = scr_cfg2.lwr;
102                cdata.int_interlaced = scr_cfg2.int;
103                cdata.lower_store_size = power_of_two (bin (scr_cfg2.size, 3) + 5);
104                if (cdata.store_b_is_lower & cdata.store_a_online) |
105                (^cdata.store_b_is_lower & cdata.store_b_online) then
106                     if scr_cfg2.nea_enabled then            /* Compute size of upper store. */
107                          cdata.upper_store_size =
108                          bin (bit (scr_cfg2.nea, 12)) - mod (cdata.base, 4096) - cdata.lower_store_size;
109                     else
110                     cdata.upper_store_size = cdata.lower_store_size;
111                else
112                cdata.upper_store_size = 0;
113                string (cdata.cyclic_priority) = scr_cfg2.cyclic_prior;
114                call interpret_eima (1, scr_cfg2.mask_a_assign);
115                call interpret_eima (2, scr_cfg2.mask_b_assign);
116                cdata.eima_data (1).mask_available,
117                     cdata.eima_data (2).mask_available = "1"b;
118                cdata.eima_data (3).mask_available,
119                     cdata.eima_data (4).mask_available = "0"b;
120 
121                cdata.program = scr_cfg2.mode;
122           end;
123 
124 ^L
125 
126           else do;                                          /* If 6000 SC ... */
127                cdata.store_a_online = (scr_cfg1.mode_a = "000"b);
128                cdata.store_b_online = (scr_cfg1.mode_b = "000"b);
129                cdata.store_b_is_lower = scr_cfg1.lwr;
130                cdata.int_interlaced = scr_cfg1.int;
131                if cdata.store_a_online then
132                     store_a_size = (bin (scr_cfg1.bdry_a, 3) + 1) * 32;
133                else
134                store_a_size = 0;
135                if store_a_size = 128 then
136                     cdata.store_a1_online = "1"b;           /* Two ports for 128K store. */
137                else
138                cdata.store_a1_online = "0"b;
139                if cdata.store_b_online then
140                     store_b_size = (bin (scr_cfg1.bdry_b, 3) + 1) * 32;
141                else
142                store_b_size = 0;
143                if store_b_size = 128 then
144                     cdata.store_b1_online = "1"b;           /* Two ports for 128K store. */
145                else
146                cdata.store_b1_online = "0"b;
147                if cdata.store_b_is_lower then do;
148                     cdata.lower_store_size = store_b_size;
149                     cdata.upper_store_size = store_a_size;
150                end;
151                else do;
152                     cdata.lower_store_size = store_a_size;
153                     cdata.upper_store_size = store_b_size;
154                end;
155                string (cdata.cyclic_priority) = (7)"0"b;
156                do i = 1 to 4;
157                     call interpret_eima (i, scr_cfg1.pima (i));
158                     cdata.eima_data (i).mask_available = "1"b;
159                end;
160 
161                cdata.program = "1"b;
162           end;
163 
164           return;
165 
166 ^L
167 
168 set_port_enable: entry (port, enable_sw);                   /* entry to enable a controller port */
169 
170 dcl  enable_sw bit (1) unal;                                /* 1 => enable corresponding port */
171 
172 
173           call set_port_enable_bit (port, enable_sw);       /* Set the bit first. */
174 
175           do ctag = 0 to 7;                                 /* Set ports in all controllers. */
176                cdp = addr (scs$controller_data (ctag));     /* Get pointer to controller data for this port. */
177 
178                if cdata.online then                         /* If controller is in use ... */
179                     call enable_ports (ctag);               /* Go set the port enable bits. */
180           end;
181 
182           return;
183 
184 
185 
186 set_port_enable_bit: entry (port, enable_sw);               /* entry to only set port enable bits */
187 
188 
189           mkp = addr (scs$sys_level);                       /* Get pointer to array of masks. */
190 
191           do i = 1 to scs$number_of_masks;                  /* Modify all masks. */
192                scrp = addr (masks (i));                     /* Get pointer to mask. */
193                if port < 4 then                             /* If ports 0 thru 3 ... */
194                     substr (scr_msk.port_mask_1, port + 1, 1) = enable_sw;
195                else                                         /* If ports 4 thru 7 ... */
196                substr (scr_msk.port_mask_2, port - 3, 1) = enable_sw;
197           end;
198 
199           return;
200 
201 ^L
202 
203 enable_ports: entry (port);                                 /* entry to set port enable bits in a controller */
204 
205 
206           cdp = addr (scs$controller_data (port));          /* Get pointer to data for this controller. */
207           scrp = addr (scs$cfg_data (port));                /* Get pointer to CFG data for this controller. */
208           mkp = addr (scs$sys_level);                       /* Get pointer to a mask. */
209 
210           if cdata.type >= "0010"b then do;                 /* If 4MW SCU ... */
211                scr_cfg2.port_mask_0_3 = mkp -> scr_msk.port_mask_1;
212                scr_cfg2.port_mask_4_7 = mkp -> scr_msk.port_mask_2;
213                call set_cfg (port);                         /* Actually set the controller. */
214           end;
215 
216           else                                              /* If 6000 SC ... */
217           if port = scs$interrupt_controller then           /* If bootload controller, allow interrupts. */
218                call privileged_mode_ut$smcm (port, scs$open_level);
219           else                                              /* If not bootload controller, prevent interrupts. */
220           call privileged_mode_ut$smcm (port, scs$sys_level);
221 
222           return;
223 
224 
225 
226 disable_ports: entry (port);                                /* entry to clear all port enable bits in a controller */
227 
228 
229           cdp = addr (scs$controller_data (port));          /* Get pointer to data for this controller. */
230           scrp = addr (scs$cfg_data (port));                /* Get pointer to CFG data for this controller. */
231 
232           if cdata.type >= "0010"b then do;                 /* If 4MW SCU ... */
233                scr_cfg2.port_mask_0_3 = "0000"b;
234                scr_cfg2.port_mask_4_7 = "0000"b;
235                call set_cfg (port);                         /* Actually set the controller. */
236           end;
237 
238           else                                              /* If 6000 SC ... */
239           call privileged_mode_ut$smcm (port, unspec (bin (0, 71)));
240 
241           return;
242 
243 ^L
244 
245 assign_mask: entry (port, target);                          /* entry to assign a mask to a port */
246 
247 dcl  target fixed bin (3);                                  /* port to which mask will be assigned */
248 
249 dcl  mask_assignment bit (9);                               /* mask assignment bits */
250 
251 
252           cdp = addr (scs$controller_data (port));          /* Get pointer to correct array element. */
253           scrp = addr (scs$cfg_data (port));                /* Get pointer to correct CFG data. */
254 
255           if cdata.type >= "0010"b then do i = 1 to 2;      /* Do this only for 4MW SCU. */
256                if ^cdata.eima_data (i).mask_assigned then do; /* Look for unused mask. */
257                     cdata.eima_data (i).mask_assignment = target;
258                     cdata.eima_data (i).mask_assigned = "1"b;
259                     mask_assignment = set_mask_assignment (target + 1);
260                     if i = 1 then                           /* Set appropriate field in CFG data. */
261                          scr_cfg2.mask_a_assign = mask_assignment;
262                     else
263                     scr_cfg2.mask_b_assign = mask_assignment;
264                end;
265           end;
266 
267           return;
268 
269 
270 
271 unassign_mask: entry (port, target);                        /* entry to unassign a mask from a port */
272 
273 
274           cdp = addr (scs$controller_data (port));          /* Get pointer to correct array element. */
275           scrp = addr (scs$cfg_data (port));                /* Get pointer to correct CFG data. */
276 
277           if cdata.type >= "0010"b then do i = 1 to 2;      /* Do this only for 4MW SCU. */
278                if cdata.eima_data (i).mask_assigned &       /* Look for mask used for this target. */
279                (cdata.eima_data (i).mask_assignment = target) then do;
280                     cdata.eima_data (i).mask_assigned = "0"b;
281                     mask_assignment = set_mask_assignment (9);
282                     if i = 1 then                           /* Set appropriate field in CFG data. */
283                          scr_cfg2.mask_a_assign = mask_assignment;
284                     else
285                     scr_cfg2.mask_b_assign = mask_assignment;
286                end;
287           end;
288 
289           return;
290 
291 
292 ^L
293 
294 reassign_mask: entry (tag1, tag2);                          /* entry to reassign mask to another port */
295 
296 dcl  tag1 fixed bin (3),                                    /* processor tag of assigned mask */
297      tag2 fixed bin (3);                                    /* processor tag for new assignment */
298 
299 
300           ctag = scs$interrupt_controller;                  /* Change bootload controller only. */
301 
302           if tag1 ^= -1 then do;                            /* If assignment to be removed ... */
303                pdp = addr (scs$processor_data (tag1));      /* Get pointer to data for this processor. */
304 
305                if tag2 ^= -1 then                           /* Check for same-port (poss. expander) case and punt */
306                     if pdata.controller_port = scs$processor_data (tag2).controller_port then return;
307                call set_mask (ctag, (pdata.controller_port), 0);
308                                                             /* Clear the mask. */
309                call unassign_mask (ctag, (pdata.controller_port));
310                                                             /* Unassign the mask. */
311           end;
312           if tag2 ^= -1 then do;                            /* If new assignment to be made ... */
313                pdp = addr (scs$processor_data (tag2));      /* Get pointer to data for this processor. */
314 
315                call assign_mask (ctag, (pdata.controller_port));
316                                                             /* Make new mask assignment. */
317                call set_cfg (ctag);                         /* Set switches in controller. */
318           end;
319 
320           return;
321 
322 ^L
323 update_export_xipmsk:
324           entry (port);                                     /* Update port-expander XIP masks */
325 
326 dcl 1 rcow based (addr (scs$reconfig_general_cow)) aligned like scs$reconfig_general_cow;
327 
328           unspec (rcow) = ""b;                              /* Zero the cow. */
329           do i = 0 to 7;
330                pdp = addr (scs$processor_data (i));         /* Address proc data element */
331                if pdata.expanded_port & pdata.controller_port = port
332                     then substr (rcow.sub_mask, pdata.expander_port + 1, 1) =  pdata.interrupt_cpu;
333           end;
334           rcow.expander_command = "2"b3;                    /* Set XIP register */
335           rcow.controller_port = port;
336           call privileged_mode_ut$cioc (addr (rcow.cow));   /* We rely on this living in the bootload controller */
337           return;
338 
339 set_export_enable:
340           entry (port, subport, enable_sw);
341 
342 dcl  subport fixed bin (3);
343 
344           unspec (rcow) = ""b;                              /* Clear out sutff */
345           do i = 0 to 7;                                    /* Scan CPU's */
346                pdp = addr (scs$processor_data (i));
347                if pdata.expanded_port & pdata.controller_port = port
348                     then if pdata.expander_port = subport
349                          then substr (rcow.sub_mask, pdata.expander_port + 1, 1) = enable_sw;
350                          else substr (rcow.sub_mask, pdata.expander_port + 1, 1) = pdata.online;
351          end;
352           substr (rcow.sub_mask, 5, 1) = "1"b;              /* T. Ohlin wants exerciser bit on. */
353          rcow.expander_command = "1"b3;                     /* Set subport enables */
354          rcow.controller_port = port;
355          call privileged_mode_ut$cioc (addr (rcow.cow));    /* Zap the bootload SCU */
356 /* The enables on all the other SCU's will be left enabled */
357          return;
358 
359 
360 ^L
361 set_cfg:  entry (port);                                     /* entry to set CFG data in controller */
362 
363 
364           if scs$controller_data (port).type >= "0010"b then do; /* If 4MW SCU ... */
365                if scs$set_cycle_switches then
366                     string (addr (scs$cfg_data (port)) -> scr_cfg2.cyclic_prior) = scs$cycle_priority_template;
367 try_to_set_cfg:
368                scrp = addr (scs$cfg_data (port));
369                unspec (port_enable_bits) = scr_cfg2.port_mask_0_3 || scr_cfg2.port_mask_4_7;
370                set_cfg_ok = "0"b;
371                do set_cfg_try_count = 1 repeat set_cfg_try_count + 1
372                     while (set_cfg_try_count <= SET_CFG_TRY_LIMIT & ^set_cfg_ok);
373                     call privileged_mode_ut$sscr (port, SC_CFG, scs$cfg_data (port));
374                     if unspec (port_enable_bits) = "0"b then set_cfg_ok = "1"b;     /* if we can't check, assume OK     */
375                     else do;
376                          call privileged_mode_ut$rscr (port, SC_CFG, scr_cfg2_temp); /* read to make sure it took       */
377                          if (unspec (scr_cfg2_temp) & SCR_CFG2_PROGRAM_MASK)
378                               = (unspec (scs$cfg_data (port)) & SCR_CFG2_PROGRAM_MASK)    /* check all program-settable bits*/
379                               then set_cfg_ok = "1"b;
380                     end;
381                end;
382 
383 /* If the sscr did not take within the requisite number of tries, we
384    punt by printing instructions to the operator to clear the SCU
385    manually.  This involves setting switches, flipping the mode into
386    MANUAL, then back into PROGRAM.  When these two actions have happened,
387    we check again, repeating the process if necessary                                                         */
388 
389                if ^set_cfg_ok then do;                      /* drastic manual intervention                    */
390                     call syserr (3, "scr_util: error setting configuration register. SCU ^a must be set manually",
391                          substr (LETTERS, port+1, 1));
392                     call syserr (0, "Set the following switches on SCU ^a",
393                          substr (LETTERS, port+1,1));
394 
395                     unspec (cycle_priority_bits) = scr_cfg2.cyclic_prior;
396                     unspec (nea_bits) = scr_cfg2.nea;
397                     mask_a_val = convert_to_mask_val (substr (scr_cfg2.mask_a_assign, 1, 8));
398                     mask_b_val = convert_to_mask_val (substr (scr_cfg2.mask_b_assign, 1, 8));
399 
400                     call syserr (0, "^/^12x--PORT ENABLE--  --CYCLIC PRIORITY---^/^12x0 1 2 3 4 5 6 7  0/1 1/2 2/3 3/4 4/5 5/6 6/7^/^8xON  ^8(^[X^; ^] ^) ^7( ^[X^; ^]  ^)^/^8xOFF ^8(^[ ^;X^] ^) ^7( ^[ ^;X^]  ^)",
401                          port_enable_bits, cycle_priority_bits,
402                          port_enable_bits, cycle_priority_bits);
403                     call syserr (0, "^/^8xNON-EXISTENT ADDRESS^/^17x2 3 4 5 6 7 8^/^8xON  ^[X^; ^]  1 ^7(^[X^; ^] ^)^/^8xOFF ^[ ^;X^]  0 ^7(^[ ^;X^] ^)",
404                          scr_cfg2.nea_enabled, nea_bits,
405                          scr_cfg2.nea_enabled, nea_bits);
406                     call syserr (0, "^/^8xSTORE A  A1 B  B1^/^8xON    ^4(^[X^; ^]  ^)^/^8xOFF   ^4(^[ ^;X^]  ^)",
407                          scr_cfg2.a_online, scr_cfg2.a1_online, scr_cfg2.b_online, scr_cfg2.b1_online,
408                          scr_cfg2.a_online, scr_cfg2.a1_online, scr_cfg2.b_online, scr_cfg2.b1_online);
409                     call syserr (0, "^/^8xLWR STORE SIZE - ^d^/^8xINTERLACE - ^[ON^;OFF^]^/^8xLWR STORE - ^[B^;A^]^/^8xMASK A - ^a^/^8xMASK B - ^a",
410                          bin (scr_cfg2.size), scr_cfg2.int, scr_cfg2.lwr,
411                          mask_a_val, mask_b_val);
412 
413                     call syserr (0, "After setting the switches for SCU ^a place SCU ^a into Manual Mode and then into Program Mode",
414                          substr (LETTERS, port+1, 1), substr (LETTERS, port+1, 1));
415 
416 /* Wait for SCU to go into Manual Mode                                                                        */
417 
418                     do while (addr (scr_cfg2_temp) -> scr_cfg2.mode);
419                          call privileged_mode_ut$rscr (port, SC_CFG, scr_cfg2_temp);
420                     end;
421 
422 /* Wait for SCU to go into Program Mode                                                                       */
423 
424                     do while (^addr (scr_cfg2_temp) -> scr_cfg2.mode);
425                          call privileged_mode_ut$rscr (port, SC_CFG, scr_cfg2_temp);
426                     end;
427 
428 
429 /* Check whether SCU cleared properly                                                                         */
430 
431                     if (unspec (scr_cfg2_temp) & SCR_CFG2_PROGRAM_MASK)
432                          ^= (unspec (scs$cfg_data (port)) & SCR_CFG2_PROGRAM_MASK)
433                          then goto try_to_set_cfg;
434                end;
435 
436 
437 
438 
439 
440           end;
441                                                             /* Set CFG data in controller. */
442           return;
443 
444 
445 
446 set_mask: entry (port, target, mask);                       /* entry to set mask for controller port */
447 
448 dcl  mask fixed bin (71);                                   /* mask to be set */
449 
450 
451           call privileged_mode_ut$sscr (port, SC_MSK + 8 * target, mask);
452                                                             /* Set the mask. */
453 
454           return;
455 
456 
457 ^L
458 
459 convert_to_mask_val:
460           proc (scu_mask_bits) returns (char (*));          /* procedure to convert a mask to printable form  */
461 
462 dcl  scu_mask_bits bit (*) unaligned,
463      mask_val pic "9";
464 
465 
466           if index (scu_mask_bits, "1"b) >0 then do;
467                mask_val = index (scu_mask_bits, "1"b) - 1;
468                return (mask_val);
469           end;
470           else return ("Off");
471 
472 
473 end convert_to_mask_val;
474 
475 
476 
477 ^L
478 
479 interpret_eima: proc (n, eima);                             /* procedure to determine port assignment from bits */
480 
481 dcl  n fixed bin,                                           /* EIMA number */
482      eima bit (9);                                          /* mask assignment bits */
483 
484 dcl  x fixed bin;                                           /* port mask assigned to */
485 
486 
487                x = index (eima, "1"b);                      /* Look for bit ON. */
488                if (x = 0) | (x = 9) then                    /* If no bits ON, or last bit ON ... */
489                     cdata.eima_data (n).mask_assigned = "0"b; /* Mask is not assigned to any port. */
490                else do;                                     /* Mask is assigned. */
491                     cdata.eima_data (n).mask_assigned = "1"b;
492                     cdata.eima_data (n).mask_assignment = x - 1; /* Remember port to which mask is assigned. */
493                end;
494 
495                return;
496 
497           end interpret_eima;
498 
499 
500 
501 set_mask_assignment: proc (n) returns (bit (9) unal);       /* procedure to set correct mask assignment bit */
502 
503 dcl  n fixed bin;                                           /* bit to be set */
504 
505 dcl  m bit (9) aligned;                                     /* prototype mask assignment bits */
506 
507 
508                m = "0"b;                                    /* Clear all bits. */
509                substr (m, n, 1) = "1"b;                     /* Set the desired bit. */
510 
511                return (m);                                  /* Return assignment bits. */
512 
513 
514           end set_mask_assignment;
515 
516 
517 ^L
518 
519 power_of_two: proc (e) returns (fixed bin);                 /* procedure to compute power of two */
520 
521 dcl  e fixed bin;                                           /* exponent */
522 
523 dcl  p fixed bin;                                           /* power of two */
524 
525 
526                p = 0;                                       /* Clear the result. */
527                substr (unspec (p), 36 - e, 1) = "1"b;       /* Very quick, and extremely dirty. */
528 
529                return (p);
530 
531 
532           end power_of_two;
533 
534 /* ^L */
535 
536 /* isolts_scu_p1 - entry to set config data in the SCU being used for ISOLTS, to isolate the processor under test */
537 
538 isolts_scu_p1: entry;
539 
540           iscu = scs$processor_test_data.scu_tag;           /* pick up scu_tag, cpu_tag, and mask cpu tag */
541           icpu = scs$processor_test_data.cpu_tag;           /* from processor test data structure */
542           mcpu = scs$processor_test_data.mask_cpu;
543           cdp = addr (scs$controller_data (iscu));
544           scrp = addr (scs$cfg_data (iscu));
545           pdp = addr (scs$processor_data (icpu));
546           mkp = addr (scs$cpu_test_mask);
547 
548 /* do the things common to both types of SCU's first */
549 
550           maska = set_mask_assignment (scs$processor_data (mcpu).controller_port + 1);
551           maskb = set_mask_assignment (pdata.controller_port + 1);
552 
553 /* set up scs$cpu_test mask */
554 
555           scs$cpu_test_mask = "0"b;                         /* initialize it first */
556           mkp -> scr_msk.port_mask_1 = substr ((maska | maskb), 1, 4); /* set port mask fields */
557           mkp -> scr_msk.port_mask_2 = substr ((maska | maskb), 5, 4);
558 
559           if cdata.type >= "0010"b then do;                 /* if 4MW SCU ... */
560 
561                scr_cfg2.mask_a_assign = maska;              /* set up config data */
562                scr_cfg2.mask_b_assign = maskb;
563                scr_cfg2.port_mask_0_3 = mkp -> scr_msk.port_mask_1;
564                scr_cfg2.port_mask_4_7 = mkp -> scr_msk.port_mask_2;
565 
566                call set_cfg ((iscu));                       /* actually set config data in SCU */
567 
568           end;
569 
570           else call privileged_mode_ut$smcm ((iscu), scs$cpu_test_mask); /* 6000 SCU, just set port mask  */
571           call set_mask ((iscu), (scs$processor_data (mcpu).controller_port), /* mask off interrupts */
572                fixed (scs$cpu_test_mask, 71));              /* in mask cpu */
573           mkp -> scr_msk.interrupt_mask_1 = "1001000000001000"b; /* set int mask for cells 0 and 12 */
574                                                             /* and cell 3 for test progras */
575           scs$processor_test_data.scu_state = "10"b;        /* set scu state to indicate where we are at */
576 
577           return;                                           /* thats all folks */
578 
579 /* ^L */
580 
581 /* isolts_scu_p2 - entry to re-enable original SCU ports + port for test cpu */
582 
583 isolts_scu_p2: entry;
584 
585           iscu = scs$processor_test_data.scu_tag;           /* pick up scu_tag, cpu_tag, and mask cpu tag */
586           icpu = scs$processor_test_data.cpu_tag;           /* from processor test data structure */
587           mcpu = scs$processor_test_data.mask_cpu;
588           cdp = addr (scs$controller_data (iscu));
589           scrp = addr (scs$cfg_data (iscu));
590           pdp = addr (scs$processor_data (icpu));
591           mkp = addr (scs$cpu_test_mask);
592 
593 /* do the things common to both types of SCU's first */
594 
595           maska = set_mask_assignment (pdata.controller_port + 1);
596           pdp = addr (scs$sys_level);                       /* get a pointer to a mask */
597           mkp -> scr_msk.port_mask_1 = pdp -> scr_msk.port_mask_1 | substr (maska, 1, 4);
598           mkp -> scr_msk.port_mask_2 = pdp -> scr_msk.port_mask_2 | substr (maska, 5, 4);
599 
600           if cdata.type >= "0010"b then do;                 /* if 4MW SCU ... */
601 
602                scr_cfg2.port_mask_0_3 = mkp -> scr_msk.port_mask_1;
603                scr_cfg2.port_mask_4_7 = mkp -> scr_msk.port_mask_2;
604 
605                call set_cfg ((iscu));                       /* actually set config data in SCU */
606 
607           end;
608 
609           else call privileged_mode_ut$smcm ((iscu),
610                "000000000017000000000017"b3 & scs$cpu_test_mask); /* 6000 SCU, set port mask */
611           call set_mask ((iscu), (scs$processor_data (mcpu).controller_port), /* mask off interrupts */
612                fixed ("000000000017000000000017"b3 & scs$cpu_test_mask, 71)); /* in mask cpu */
613 
614           return;                                           /* thats all folks */
615 
616 
617 /* ^L */
618 
619 /* isolts_scu_p3 - entry to restore orignial SCU port masks upon termination of ISOLTS CPU testing */
620 
621 isolts_scu_p3: entry;
622 
623           iscu = scs$processor_test_data.scu_tag;           /* pick up scu_tag */
624           cdp = addr (scs$controller_data (iscu));
625 
626           scs$cfg_data (iscu) = scs$cfg_data_save;          /* restoe orignial config data */
627 
628           if cdata.type >= "0010"b then                     /* if 4MW SCU */
629                call set_cfg ((iscu));                       /* actually set config data */
630           else call privileged_mode_ut$smcm ((iscu), scs$sys_level); /* if 6000 SC */
631 
632           return;                                           /* thats all */
633 
634 %page;
635 /* BEGIN MESSAGE DOCUMENTATION
636 
637    Message:
638    scr_util: error setting configuration register. SCU X must be set manually.
639    Set the following switches on SCU X
640    < Diagram of SCU Maintenance Panel is Printed Here>
641    After setting the switches for SCU X place SCU S into Manual Mode and then into Program Mode
642 
643    S: $beep
644 
645    T: Reconfiguration (e.g., adding or deleting a CPU)
646 
647    M: The supervisor was unable to set the configuration register in the SCU
648    indicated after 10 attempts.  To avoid a system crash, the SCU must be
649    cleared manually.  In this message, the supervisor will print a diagram
650    of the SCU Maintenance Panel, indicating how each switch should be set.
651 
652    A: The operator should copy the diagram of the SCU Maintenance Panel
653    printed by the supervisor (or take the copy printed, if possible).  The
654    operator should then go to the Maintenance Panel of the SCU indicated
655    and set each switch on the diagram to the indicated position, and then
656    verify that each switch is in the correct position.  Following this, the
657    operator should set the Program/Manual switch into the Manual position
658    briefly, and then return it to the Program position.  If this procedure
659    does not remedy the problem, the message will be repeated, and the
660    System Programming Staff should be contacted.
661 
662    END MESSAGE DOCUMENTATION */
663 
664      end scr_util$read_cfg;