1 " ***********************************************************
2 " * *
3 " * Copyright, C Honeywell Bull Inc., 1987 *
4 " * *
5 " * Copyright, C Honeywell Information Systems Inc., 1984 *
6 " * *
7 " * Copyright, C Honeywell Information Systems Inc., 1982 *
8 " * *
9 " * Copyright c 1972 by Massachusetts Institute of *
10 " * Technology and Honeywell Information Systems, Inc. *
11 " * *
12 " ***********************************************************
13
14 "
15 " cache_priv - privileged subroutine to perform static test of cache memory.
16 " Called from pl1 procedure cache_tester.
17 "
18 " Entry description:
19 "
20 " dcl cache_priv$csh1 csh2 entry ptr fixed bin ptr fixed bin 35;
21 " call cache_priv$csh1 csh2 wired_buf_ptr buf_size info_ptr code;
22 "
23 " where:
24 "
25 " 1. wired_buf_ptr - is a ptr to a wired encachable buffer. It is assumed that the
26 " wired buffer has been filled with the desired test data pattern, by the caller.
27 "
28 " 2. buf_size - is the buffer size in words. It should be one half the cache size.
29 "
30 " 3. info_ptr - is a ptr to a wired info structure which is a 3 element array of
31 " error/diagnostic info. The structure array elements are defined below. The data
32 " from the first 3 errors encountered is stored in the info structure.
33 "
34 " 4. code - is an indication of the existance of a cache error, and is also the
35 " count of the number of errors encounterd.
36 "
37 " The cache_priv$csh1 entry is to test the lower half of cache memory defined by
38 " the program settable switch "csh1" in the cache mode register. The
39 " cache_priv$csh2 entry is to test the upper half of cache memory defined by the
40 " program settable switch "csh2" in the cache mode register.
41 "
42 " Original coding by J. A. Bush 1/15/80
43 " Modified by J. A. Bush 6/20/80 to not inhibit so long
44 "
45 " Modified by R. A. Fawcett June 1984 to handle:
46 " 1. Original type of DPS8M 8K cache
47 " 2. VSSC cache for 8K 16K and 32K configs
48 " 3. And do the same things for all types of CACHE including L68 2K.
49 " After the above changes Bush would not recognize this program.
50 "
51 name cache_priv
52 entry csh1
53 entry csh2
54
55 tempd maskwd,ptwp,arglist7 arguments for calls
56 tempd temp_fault_reg temp storage for fault reg
57 tempd cam_wait
58 temp buf_length storage for cache buffer length
59 temp temp_ind_reg temp storage for ind reg
60 temp timer temp storage for the timer register
61 temp not_me
62 " The next equs are for the cpriv_info.err_data array in cache_tester.
63 " They are based on the bb indexed by x4 and there are 3 possible error sets.
64
65 equ cache_data,0 error data in cache
66 equ ex_or_data,2 exclusive or of error data in memory and cache
67 equ fault_reg,4 storage for fault register
68 equ cache_addr,6 storage for error address in cache
69 equ ind_reg,7 storage for indicator register
70
71
72 bool par_err,1000 parity indicator
73 bool par_mask,400 parity mask indicator
74
75
76 csh1:
77 "**** entry to test lower half of cache ***
78 push
79 eax3 0 set cache on constant to csh1
80 tra c_com
81
82
83 csh2:
84 "**** entry to test upper half of cache ***
85 push
86 eax3 1 set cache on constant to csh2
87
88 c_com:
89 eppbp ap|2,* get cache buf ptr
90 eppbp bp|0,*
91 eppbb ap|6,* get com region address
92 eppbb bb|0,*
93
94 lxl7 ap|4,* get buffer size in words
95 stx7 buf_length and save for comparisons
96 eaa 0,x7 calc clear time based on cache size
97 arl 3
98 eax4 0,au initialize csh_on wait count
99 eax6 0 start at address 0 of buffer
100
101
102 epplb page$cam_wait
103 sprilb cam_wait
104
105 epplb maskwd " mask so that no interups are taken
106 sprilb arglist+2
107 epplb ptwp
108 sprilb arglist+4
109 ldaq TWO_ARGS_ND
110 staq arglist
111 call pmut$wire_and_maskarglist
112
113 ldi par_mask,dl don't take parity fault
114
115 stt timer save the current timer
116 ldt TIMER set timer for 4min + no fault
117
118
119 prev_connects:
120 epplb ptwp
121 sprilb arglist+2
122 ldaq ONE_ARG_ND
123 staq arglist cause other cpus to loop unitl
124 call cam_wait,*arglist cache is loaded
125
126 clear_cache:
127
128 lcpr csh_off,02 insure that cache is OFF
129 xec csh_on,3 turn appropriate cache segment on
130 eax4 -1,4 wait for cache hardware initialization
131 nop 0,du
132 tnz *-2 error counter x4 is 0 on loop exit
133
134 l_loop:
135 ldaq bp|0,6 fill cache by referencing wired buffer
136 eax6 4,6 increment to next block address
137 eax7 -4,7 decrement block count
138 tnz l_loop xfer if not full
139 lcpr csh_off,02 now turn cache off
140
141 stz scs$cam_wait trun others lose
142
143 set_up_check:
144 ldi 0,dl initialize indicator reg
145 eax6 0 all done initialize buffer index
146 cmpx3 1,du are we testing upper cache memory?
147 tnz c_loop xfer if no, x7 has address 0 start of lower cache
148 ldx7 buf_length yes set cache read address to upper half
149
150 c_loop:
151 inhibit on
152 ldi par_mask,dl don't take parity fault here!!!
153 lcpr cache_to_reg_mode,02
154 ldaq bp|0,7 load data from cache
155 lcpr csh_off,02 turn reg mode off
156 inhibit off
157 sti temp_ind_reg save indicator reg
158 ldi 0,dl and initialize
159
160 cmpaq bp|0,6 data in cache equal to data in mem?
161 tze par_chk xfer if yes
162 cmpaq csh_off data in cache = csh_off constant?
163 tnz cmp_err xfer if no
164
165 par_chk:
166 lxl5 temp_ind_reg but did we have a parity error?
167 canx5 par_err,du
168 tnz cmp_err xfer if yes
169
170 err_cont:
171 eax7 2,7 increment cache address
172 eax6 2,6 increment memory address
173 cmpx6 buf_length last cache addr looked at
174 tmi c_loop xfer if no
175 ldi 0,dl yes, reset parity mask
176 eaa 0,4 copy error index to a
177 arl 18+3 right justify and get real error count
178 sta ap|8,* and store in error code
179
180
181 epplb maskwd now we can unmask
182 sprilb arglist+2
183 epplb ptwp
184 sprilb arglist+4
185 ldaq TWO_ARGS_ND
186 staq arglist
187 call pmut$unwire_unmaskarglist unmask
188
189 ldt timer restore_timer
190 return all done this half
191
192 cmp_err:
193
194 cmpx4 24,du do we have 3 errors already?
195 tmi capture no, go capture error data
196 eax4 8,4 yes, just add 1 more to error count
197 tra err_cont and go loop trough rest of cache
198
199 capture:
200 scpr temp_fault_reg,01 compare/parity error, save fault reg
201 staq bb|cache_data,4 save cache data
202 eraq bp|0,6 exclusive or cache and memory data
203 staq bb|ex_or_data,4
204 lxl5 temp_ind_reg but did we have a parity error?
205 anx5 par_err,du
206 sxl5 bb|ind_reg,4 save indicator reg of error
207 lda temp_fault_reg save fault reg
208 sta bb|fault_reg,4
209 sxl7 bb|cache_addr,4 save cache address in error
210 eax4 8,4 add 1 more to error count
211 tra err_cont and go loop trough rest of cache
212
213 inhibit on
214 even
215 csh_on: lcpr csh1_on,02 turn csh1 on with xec instruction
216 lcpr csh2_on,02 turn csh2 on with xec instruction
217 inhibit off
218
219 csh1_on: oct 500003 csh1 and operands on
220 csh2_on: oct 300003 csh2 and operands on
221
222 even
223 csh_off: oct 3
224 oct 707070707070 pattern to ignore csh_off constant
225
226 cache_to_reg_mode:
227 oct 10003 cache dump mode
228
229 even
230 ONE_ARG_ND:
231 zero 2,2
232 zero 0,0
233 TWO_ARGS_ND:
234 zero 4,4
235 zero 0,0
236
237 TIMER: oct 777777777777
238 end