1 " ***********************************************************
2 " * *
3 " * Copyright, C Honeywell Bull Inc., 1987 *
4 " * *
5 " * Copyright, C Honeywell Information Systems Inc., 1982 *
6 " * *
7 " * Copyright c 1972 by Massachusetts Institute of *
8 " * Technology and Honeywell Information Systems, Inc. *
9 " * *
10 " ***********************************************************
11
12 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
13 " "
14 " cam_cache "
15 " "
16 " Subroutine to clear ptw associative memory and optionally"
17 " cache memory on this and all other processors. "
18 " The subroutine will not return until this has been "
19 " accomplished. "
20 " "
21 " This subroutine has two sets of entry points. One set "
22 " consists of entry points callable only from within "
23 " bound_page_control via tsx7. For these, arguments are "
24 " passed via the pxss/page_fault stack frame. The other "
25 " set consists of entry points callable externally via "
26 " the transfer-module page. For these arguments are "
27 " passed in the usual PL/1 manner. "
28 " "
29 " The only possible parameter to cam_cache entry points is "
30 " an absolute memory address for selective cache clearing "
31 " For calls from within bound_page_control this address is "
32 " passed in cell core_add in the stack frame. For external "
33 " calls the PTW of the page containing the target address "
34 " for selective clearing is passed in Argument 1. "
35 " "
36 " The functions performed by the subroutine are as follows "
37 " with the internal and external entry points: "
38 " "
39 " Clear all ptw associative memory selectively clear cache "
40 " cam_cache internal "
41 " cam_cache_ext external "
42 " "
43 " Clear all ptw associative memory clear all cache "
44 " cam internal "
45 " cam_ext external "
46 " "
47 " Clear all ptw associative memory "
48 " cam_ptws internal "
49 " cam_ptws_ext external "
50 " "
51 " Clear all ptw associative memory selectively clear cache "
52 " set scs$cam_wait so that all other processors wait "
53 " for scs$cam_wait to be cleared before resuming. "
54 " cam_with_wait internal "
55 " cam_with_wait_ext external "
56 " "
57 "^L
58 " "
59 " The protocol for multi-processor clearing is as follows: "
60 " "
61 " This processor obtains the connect lock. "
62 " "
63 " Under the connect lock the processor "
64 " 1. sets scs$cam_pair to the instructions "
65 " which do the clearing "
66 " 2. sets the scs$fast_cam_pending cell "
67 " non-zero for all other processors "
68 " 3. if this is a cam-with-wait call sets "
69 " the appropriate bit in scs$cam_wait for "
70 " all other processors "
71 " 4. sends a connect to all other processors "
72 " 5. XED's the code in scs$cam_pair "
73 " 6. waits for all scs$fast_cam_pending cells "
74 " to clear indicating clearing done by "
75 " all other processors. "
76 " 7. releases the connect lock and returns "
77 " Note - if only one processor is active most "
78 " of this is skipped. "
79 " "
80 " Upon receipt of a connect all other processors "
81 " 1. if its scs$fast_cam_pending cell is set "
82 " XED the code in scs$cam_pending and "
83 " clear it scs$fast_cam_pending cell "
84 " 2. if its bit in scs$cam_wait is set wait "
85 " for that bit to clear this clearing is "
86 " done by the caller of cam_cache on the "
87 " originating processor. "
88 " "
89 " "
90 " There are only two ways a conect fired to another "
91 " processor can be lost. One is hardware failure and the "
92 " other is a processor put into step mode before the connect "
93 " and taken out of step mode after the connect. There is "
94 " a hedge against the latter here. If all processors have "
95 " not responded within an unreasonable amount of time the "
96 " connects are re-issued and the waiting begins anew. "
97 " This hedge should not be construed as implicitly condoning "
98 " putting a cpu on a multi-processor in step mode. It may "
99 " help in truly strange circumstances. "
100 " "
101 " "
102 " This code was copied from page_fault and modified for "
103 " fast connects by J. Bongiovanni in February 1981. "
104 " Modified September 1983 E. N. Kittlitz per S. Harris "
105 " UNCA to not destroy temp_2/x0 if lock contention "
106 " "
107 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
108
109 name cam_cache
110 segdef cam_cachecam_cache_ext
111 segdef camcam_ext
112 segdef cam_ptwscam_ptws_ext
113 segdef cam_with_waitcam_with_wait_ext
114
115 iftarget adp
116 warn WARNING: cam_cache has not been converted for the ADP.
117 ifend
118
119 channel_mask_set:
120 oct 1717
121
122 "^L
123 cam_cache_ext: " external entry for coreadd cache clear
124 stz pds$temp_2 turn off wait flag
125 lda ap|2* PTW is passed in
126 tsx7 cj1b merge with common code
127 .rt: short_return " exit
128
129 cam_cache: " entry to cam and clear cache
130 stz pds$temp_2 turn off wait flag
131 cj1a: lda core_add put core_add in pds
132 als coreadd_to_ptw.ls shift to AU
133 cj1b: ana ptw_add_maskdu mask extraneous bits
134 sta pds$temp_1
135 eax0 0 set flag for PTW clear with cache
136 tra cam_join_1 join common code
137
138 cam_ext: push
139
140 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+>
141 lxl1 prds$processor_tag get set for masking
142 lprpab scs$mask_ptr1
143 xec scs$read_mask1
144 staq temp
145 lxl1 prds$processor_tag we may have lost the processor
146 lprpab scs$mask_ptr1
147 ldaq scs$sys_level
148 xec scs$set_mask1
149
150 tsx7 cam join common code
151
152 ldaq temp retrieve previous mask
153 oraq channel_mask_set turn on all channel mask
154 anaq scs$open_level turn off unconfigured channel mask bits
155 lxl1 prds$processor_tag
156 lprpab scs$mask_ptr1
157 xec scs$set_mask1
158 inhibit off <-><-><-><-><-><-><-><-><-><-><-><->
159
160 return
161
162 cam: "camp and cams clear all cache
163 eax0 4
164 tra cam_join_0 set switch not to full Cam
165
166 cam_with_wait_ext:
167 stc1 pds$temp_2 " external entry issue a cam
168 " and set scs$cam_wait
169 eax7 .rt
170 lda ap|2*
171 tra cj1b
172
173 cam_with_wait: " entry from evict_page
174 stc1 pds$temp_2 set wait flag
175 tra cj1a
176
177 cam_ptws_ext: " remove only PTWs from AMs
178 eax7 .rt
179 cam_ptws:
180 eax0 2
181
182 cam_join_0:
183 stz pds$temp_2 set no wait sw
184 cam_join_1:
185 nop 0du allow for lockup fault reset other CPU connect
186 nop 0du ditto
187 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+>
188 lda prds$processor_pattern exclude this processor
189 era =-1 ..
190 ana scs$processor find which processors are running
191 tnz hard_cam hard case multiple processors
192
193 ldx1 pds$temp_1 prepare for cache selective cam if needed
194 xed cam_table0 execute proper type of cam
195 tra 07
196
197 hard_cam:
198 lda pds$processid lock the connect lock
199 stac scs$connect_lock ..
200 tnz cam_join_1 wait on other CPU without destroying x0 temp_2
201 szn pds$temp_2 see if waiting case
202 tze wait_join tra if no
203 lda prds$processor_pattern set flags for other processors
204 era =-1 ..
205 ana scs$processor but not for this processor
206 sta scs$cam_wait set key word in scs
207
208 wait_join:
209 eax0 00 test xr0 for coreadd case
210 tze hard_cam_with_coreadd
211 ldaq cam_table0 access proper cams
212 tra cam_join_2
213
214 hard_cam_with_coreadd:
215 ldaq cam_other_for_cache get instructions for relocation
216 ora pds$temp_1 insert selective clear addr
217 cam_join_2:
218 staq scs$cam_pair set up for all cpu's
219 repeat:
220 eax0 0 start counting with 0
221 ldq 0dl keep track of array size
222 lda prds$processor_pattern set up for all processors
223 era =-1 except us
224 ana scs$processor which are running
225 nextp: stz scs$fast_cam_pending0 clear cell just in case
226 tpl missing processor not running or am us
227 stc1 scs$fast_cam_pending0 flag for cam/cache clear
228 cioc scs$cow_ptrs0* send connect
229 missing: eax0 10 bump to next processor
230 adq 4dl bump array size in chars
231 als 1 shift bit pattern to next cpu high
232 tnz nextp more processors running
233 xed scs$cam_pair clear our own
234
235 inhibit off <-><-><-><-><-><-><-><-><-><-><-><->
236 lda 1000dl bail-out of loop limit
237 epplb scs$fast_cam_pending array of check-off cells
238 wait: sba 1dl one more loop
239 tmi repeat try entire cycle again
240 cmpc prrlfill0 check entire array clear
241 desc9a 00
242 desc9a lb|0ql
243 nop
244 nop
245 tnz wait all cells haven't cleared
246
247 lda 0dl clear the connect lock now
248 ansa scs$connect_lock ..
249 tra 07
250
251 even
252 cam_table: "table of appropriate CAM pairs
253 camp 41 "clear selective cache and ptws
254 nop
255
256 camp "clear just ptws
257 nop
258
259 camp "clear ptws
260 cams 4 "and all cache
261
262 cam_other_for_cache:
263 camp 4 "clear selective cache and ptws
264 nop 0du
265
266 "^L
267 include pxss_page_stack
268 include page_info
269
270 end
271