1 /* ***********************************************************
2 * *
3 * Copyright, C Honeywell Bull Inc., 1987 *
4 * *
5 * Copyright, C Honeywell Information Systems Inc., 1984 *
6 * *
7 * Copyright c 1972 by Massachusetts Institute of *
8 * Technology and Honeywell Information Systems, Inc. *
9 * *
10 *********************************************************** */
11
12
13 /* SCS - The System Communications Segment
14 modified 3/27/77 by Noel I. Morris
15 last modified 4/26/78 by J. A. Bush for processor testing
16 Modified 2/79 by BSG for 8-cpu port expander
17 Modified 9/16/80 by J. A. Bush for the DPS8/70M CPU
18 Modified 1/09/81 W. Olin Sibert to remove all initializations to scs_and_clock_init
19 Modified 01/16/81 W. Olin Sibert, to add scs$port_data
20 Modified Jabuary 1981 by C. Hornig for new I/O.
21 Modified 2/22/81 by J. Bongiovanni for fast connect code
22 Modified 4/23/81 by J. Bongiovanni for cycle_priority_template
23 Modified 4/09/82 by J. Bongiovanni for switch 0, processor_data_switch_value
24 Modified 7/30/82 by J. Bongiovanni for trouble_processid
25 Modified 4/11/83 by E. N. Kittlitz for drl_message_pointer.
26 Modified 10/25/83 by Keith Loepere for start_of_scs
27 */
28
29 scs:
30 procedure;
31
32 /* Static */
33
34 dcl exclude_pad 1 char 32 static options constant init "pad*";
35
36 /* Automatic */
37
38 dcl code fixed bin 35;
39 dcl 1 cdsa aligned like cds_args;
40 dcl i fixed bin;
41
42 /* Builtins */
43
44 dcl addr bin bit null size string unspec builtin;
45
46 /* Entries */
47
48 dcl create_data_segment_ entry ptr fixed bin 35;
49 %page;
50 dcl 1 scs aligned, /* Information about system controllers */
51 2 start_of_scs fixed bin 71,
52 2 controller_data 0:7 aligned like scs$controller_data,
53 /* per-controller info */
54 /* Information about CPUs */
55 2 processor_data 0:7 aligned like scs$processor_data,
56 /* information about CPUs in the system */
57 2 port_data 0:7 like scs$port_data aligned, /* Info on what is connected to each SCU port */
58 2 cow 0:7 like scs$cow, /* Actual COW's. */
59 2 cow_ptrs 0:7 aligned like scs$cow_ptrs, /* Rel pointers to COW's. */
60 2 reconfig_general_cow aligned like scs$reconfig_general_cow,
61 /* Used for reconfiguration operations */
62 /* MASKS and PATTERNS */
63 2 sys_level aligned bit 72, /* mask used while handling I/O interrupts */
64 2 open_level aligned bit 72, /* mask used during normal operation */
65 2 processor_start_mask aligned bit 72, /* mask used when starting up a CPU */
66 2 cpu_test_mask aligned bit 72, /* mask used for ISOLTS CPU testing */
67 2 number_of_masks fixed bin, /* number of masks starting at sys_level */
68 2 processor_start_pattern bit 36 aligned, /* SMIC pattern used to send processor start interrupt */
69 2 cpu_test_pattern bit 36 aligned, /* SMIC pattern used for ISOLTS processor testing */
70 2 expanded_ports bit 1 unaligned dim 0:7, /* Which ports have expanders */
71 /* CAM and CACHE clear info */
72 2 cam_pair fixed bin 71, /* instructions XEDd when CAMing and clearing CACHE */
73 2 cam_wait bit 8 aligned, /* Used when evicting pages from main memory */
74 2 pad1 fixed bin, /* MASKING INSTRUCTIONS & POINTERS */
75 2 set_mask 0:7 bit 36 aligned, /* instructions to set mask STAQ or SMCM */
76 2 read_mask 0:7 bit 36 aligned, /* instructions to read mask LDAQ or RMCM */
77 2 mask_ptr 0:7 ptr unaligned, /* pointers for real or simulated masks */
78 /* MISCELLANEOUS */
79 2 idle_aptep 0:7 ptr unaligned, /* pointer to idle process APTE for each processor */
80 2 connect_lock bit 36 aligned, /* lock for sending connects */
81 2 reconfig_lock bit 36 aligned, /* lock used during reconfiguration */
82 2 trouble_flags bit 8 aligned, /* checkoff flags for sys_trouble stopping */
83 2 bos_restart_flags bit 8 aligned, /* checkoff flags for restarting after sys_trouble */
84 2 nprocessors fixed bin, /* number of processors online */
85 2 bos_processor_tag fixed bin 3, /* CPU tag of processor running BOS */
86 2 faults_initialized bit 1 aligned, /* ON after faults have been enabled */
87 2 sys_trouble_pending bit 1 aligned, /* sys_trouble event is pending in the system */
88 2 fast_cam_pending 0:7 bit 36 aligned, /* checkoff flags for cam connect */
89 2 interrupt_controller fixed bin 3, /* port number of low order controller */
90 2 cycle_priority_template bit 7 aligned,
91 2 set_cycle_switches bit 1 aligned,
92 2 processor_start_int_no fixed bin 5, /* interrupt cell for starting a processor */
93 2 processor bit 8 aligned, /* bits ON for online CPUs */
94 2 processor_start_wait bit 8 aligned, /* checkoff flags for waiting for new processor */
95 2 trouble_processid bit 36 aligned, /* processid causing crash */
96 2 drl_message_pointer ptr unal, /* pointer to DRL message text */
97 2 processor_test_data aligned like scs$processor_test_data,
98 /* info for cpu testing */
99 2 pad2 fixed bin,
100 2 trouble_dbrs 0:7 fixed bin 71, /* DBR values at system crash time */
101 2 port_addressing_word 0:7 bit 3 aligned, /* active module port number for each controller */
102 2 cfg_data 0:7 fixed bin 71, /* RSCR-CFG data from each controller */
103 2 cfg_data_save fixed bin 71, /* RSCR-CFG save area for ISOLTS CPU testing */
104 2 processor_switch_data 0:4 bit 36 aligned, /* actual processor RSW data */
105 2 processor_switch_template 0:4 bit 36 aligned, /* expected data from RSW 0 thru 4 */
106 2 processor_switch_compare 0:4 bit 36 aligned, /* discrepancies from expected data */
107 2 processor_switch_mask 0:4 bit 36 aligned, /* masks for comparing switch data */
108 2 processor_data_switch_value bit 36 aligned, /* Correct value of CPU data switches */
109 /* Data used by init_sst and collect_free_core, from config cards. */
110 2 controller_config_size 0:7 fixed bin 14 aligned,/* config card-stated size of controller */
111 2 reconfig_locker_id char 32 aligned, /* process group ID of process doing reconfiguration */
112 2 scas_page_table 0:31 bit 36 aligned, /* Page table for SCAS */
113 2 end_of_scs fixed bin; /* For initialization */
114 %page;
115 unspec scs = "0"b; /* clear entire structure */
116
117 /* Now set up for call to create_data_segment_ */
118
119 cdsa.sections 1.p = addr scs;
120 cdsa.sections 1.len = size scs;
121 cdsa.sections 1.struct_name = "scs";
122
123 cdsa.seg_name = "scs";
124 cdsa.num_exclude_names = 1;
125 cdsa.exclude_array_ptr = addr exclude_pad;
126
127 string cdsa.switches = "0"b;
128 cdsa.switches.have_text = "1"b;
129
130 call create_data_segment_ addr cdsa code;
131 return;
132 %page;
133 %include scs;
134 %include cds_args;
135
136 end scs;