1 " ***********************************************************
2 " * *
3 " * Copyright, C Honeywell Bull Inc., 1987 *
4 " * *
5 " * Copyright, C Honeywell Information Systems Inc., 1982 *
6 " * *
7 " ***********************************************************
8
9 " HISTORY COMMENTS:
10 " 1) change86-04-03Fawcett, approve86-04-03MCR7246,
11 " audit86-04-03Farley, install86-04-07MR12.0-1036:
12 " Correct ignore_fault to work in append mode.
13 " END HISTORY COMMENTS
14
15
16 "
17 " BOOTLOAD_FAULTS
18 "
19 " This module is used to initialize the fault and interrupt vectors
20 " for running in bound_bootload_0. It ignores all interrupts, and
21 " some faults. All other faults are directed to bootload_error.
22 "
23 " Created from bootstrap1 and FWLOAD, 10/04/80 W. Olin Sibert
24 " Cleaned up and modified for bootload_error, 12/14/80 WOS
25 "
26 " Entrypoint: tsx2 bootload_faults$init
27 " Ignore SCU data at: bootload_faults$ignore_scu
28 " Interrupts ignored by: bootload_faults$ignore_fault
29 "
30
31 name bootload_faults
32 decor L68
33
34 include bootload_equs
35 include fault_vector
36
37 "^L
38
39 " Initialize all fault and interrupt pairs to SCU, TRA pair.
40 " Increment addresses in each instruction to reference different
41 " ITS pairs later in fault_vector.
42 "
43 even
44
45 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+><+><+>
46 interrupt_pair: " SCU/TRA pair for interrupts, executed in
47 scu fv.i_scu_ptr,* " absolute mode.
48 tra fv.i_tra_ptr,*
49 fault_pair: " and another pair for faults
50 scu fv.f_scu_ptr,*
51 tra fv.f_tra_ptr,*
52 inhibit off <-><-><-><-><-><-><-><-><-><-><-><-><-><->
53
54
55 segdef init
56 init: Bpush
57
58 eax7 0 " X7 is offset of current vector. We set
59 " up all the vectors and ITS pairs in parallel
60
61 loop: eaa 0,x7 " Put the offset in the AQ, to and pick up the
62 eaq 0,x7 " instruction pair. Each vector pair indirects
63 adlaq interrupt_pair " through a different set of ITS pairs later in
64 staq fv|fv.ipair,x7 " the fault_vector, one for the SCU and one for
65 " the transfer. The addresses in the vector
66 eaa 0,x7 " instructions are all absolute, relative to the
67 eaq 0,x7 " known absolute location of the fault_vector
68 adlaq fault_pair " segment. These instructions never change from
69 staq fv|fv.fpair,x7 " now on -- only the pointers are modified.
70
71 epp6 bootload_error$unexpected_scu " Now, initialize the ITS pointers for the
72 spri6 fv|fv.f_scu_ptr,x7 " SCUs and transfers
73 epp6 bootload_error$unexpected_fault
74 spri6 fv|fv.f_tra_ptr,x7
75
76 epp6 bootload_faults$ignore_scu " Fake external references, which will be
77 spri6 fv|fv.i_scu_ptr,x7 " fixed up by the binder.
78 epp6 bootload_faults$ignore_fault
79 spri6 fv|fv.i_tra_ptr,x7
80
81 adlx7 2,du " On to the next vector
82 cmpx7 64,du " of which there are but 32
83 tnz loop
84
85 " ^L
86
87 epp6 bootload_faults$ignore_scu " Now, change to treat lockup faults and
88 spri6 fv|fv.f_scu_ptr+FAULT_NO_TRO*2 " timer runouts like interrupts
89
90 epp6 bootload_faults$ignore_fault
91 spri6 fv|fv.f_tra_ptr+FAULT_NO_TRO*2
92
93 Breturn
94
95 "
96 " Following is the data area for ignoring faults, and the instruction to do it.
97 "
98
99 segdef ignore_scu
100 segdef ignore_fault
101
102 eight " Align for SCU data
103 ignore_scu:
104 bss ,8
105 pointers_and_lengths:
106 bss ,8
107
108 inhibit on <+><+><+><+><+><+><+><+><+><+><+><+><+><+><->
109 ignore_fault: " Come here to do nothing
110 spl pointers_and_lengths
111 lpl pointers_and_lengths
112 rcu ignore_scu " Complicated, isn't it?
113 inhibit off <-><-><-><-><-><-><-><-><-><-><-><-><-><-><->
114
115 end