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26 rsw_util: proc;
27
28 dcl tag fixed bin (3),
29 enabled bit (1) aligned,
30 base fixed bin (17),
31 size fixed bin (17),
32 interlace fixed bin (3);
33
34 dcl rsw_1_3_data bit (36) aligned,
35 rsw_2_data bit (36) aligned,
36 rsw_4_data bit (36) aligned,
37 (rsw2p, rsw4p) ptr,
38 rsw fixed bin (3);
39
40 dcl privileged_mode_ut$rsw entry (fixed bin (3), bit (36) aligned);
41
42 dcl (addr, bin, divide) builtin;
43
44 dcl pip ptr;
45
46 dcl 1 pi like rsw_1_3.port_info based (pip) unal;
47 ^L
48 % include rsw;
49 ^L
50 % include scs;
51
52 ^L
53
54 port_info: entry (tag, enabled, base, size, interlace);
55
56
57 rsw2p = addr (rsw_2_data);
58 rswp = addr (rsw_1_3_data);
59 call privileged_mode_ut$rsw (2, rsw_2_data);
60 if rsw2p -> dps8_rsw_2.cpu_type = 1 then do;
61 if tag > 3 then do;
62 enabled = "0"b;
63 return;
64 end;
65 pip = addr (rsw_1_3.port_info (tag));
66 call privileged_mode_ut$rsw (1, rsw_1_3_data);
67 size = divide (dps8_mem_size_table (pi.mem_size), 1024, 17, 0);
68 base = bin (pi.port_assignment, 3) * size;
69 if pi.interlace_enable then
70 if rsw2p -> dps8_rsw_2.interlace_info (tag) then
71 interlace = 2;
72 else interlace = 4;
73 else interlace = 0;
74 end;
75 else do;
76 rsw4p = addr (rsw_4_data);
77 if tag < 4 then do;
78 rsw = 1;
79 pip = addr (rsw_1_3.port_info (tag));
80 end;
81 else do;
82 rsw = 3;
83 pip = addr (rsw_1_3.port_info (tag - 4));
84 end;
85 call privileged_mode_ut$rsw (rsw, rsw_1_3_data);
86 call privileged_mode_ut$rsw (4, rsw_4_data);
87 size = divide (dps_mem_size_table (pi.mem_size), 1024, 17, 0);
88 base = bin (pi.port_assignment, 3) * size;
89 if rsw4p -> rsw_4.half (tag) then
90 size = divide (size, 2, 17, 0);
91 if pi.interlace_enable then
92 if rsw4p -> rsw_4.four (tag) then
93 interlace = 2;
94 else interlace = 4;
95 else interlace = 0;
96 end;
97 enabled = pi.port_enable;
98
99 return;
100 ^L
101
102 set_rsw_mask: entry (tag, enabled);
103
104
105 if tag < 4 then do;
106 rswp = addr (scs$processor_switch_mask (1));
107 pip = addr (rsw_1_3.port_info (tag));
108 end;
109 else do;
110 rswp = addr (scs$processor_switch_mask (3));
111 pip = addr (rsw_1_3.port_info (tag - 4));
112 end;
113
114 pi.port_enable = enabled;
115
116 return;
117
118
119
120 init_rsw_mask: entry (tag, enabled);
121
122
123 if tag < 4 then do;
124 rswp = addr (scs$processor_switch_mask (1));
125 pip = addr (rsw_1_3.port_info (tag));
126 end;
127 else do;
128 rswp = addr (scs$processor_switch_mask (3));
129 pip = addr (rsw_1_3.port_info (tag - 4));
130 end;
131
132 pi.port_assignment = "111"b;
133 pi.interlace_enable = "1"b;
134 pi.mem_size = 7;
135 pi.port_enable = enabled;
136
137 rswp = addr (scs$processor_switch_mask (4));
138 rsw_4.four (tag) = "1"b;
139 rsw_4.half (tag) = "1"b;
140
141 if tag < 4 then do;
142 rswp = addr (scs$processor_switch_template (1));
143 pip = addr (rsw_1_3.port_info (tag));
144 end;
145 else do;
146 rswp = addr (scs$processor_switch_template (3));
147 pip = addr (rsw_1_3.port_info (tag - 4));
148 end;
149
150 pi.port_enable = "1"b;
151
152 return;
153
154
155
156 end rsw_util;