1 /****^  ***********************************************************
  2         *                                                         *
  3         * Copyright, (C) Honeywell Bull Inc., 1987                *
  4         *                                                         *
  5         * Copyright, (C) Honeywell Information Systems Inc., 1982 *
  6         *                                                         *
  7         *********************************************************** */
  8 /* RSW_UTIL - Procedures to Read and Interpret the Processor Switches.
  9    coded 4/12/76 by Noel I. Morris
 10    Modfified 9/04/80 by J. A. Bush for the DPS8/70M CPU
 11 */
 12 
 13 
 14 /* ******************************************************
 15    *                                                    *
 16    *                                                    *
 17    * Copyright (c) 1972 by Massachusetts Institute of   *
 18    * Technology and Honeywell Information Systems, Inc. *
 19    *                                                    *
 20    *                                                    *
 21    ****************************************************** */
 22 
 23 
 24 
 25 
 26 rsw_util: proc;
 27 
 28 dcl  tag fixed bin (3),                                     /* system controller tag */
 29      enabled bit (1) aligned,                               /* "1"b if processor port enabled */
 30      base fixed bin (17),                                   /* base address of memory in controller */
 31      size fixed bin (17),                                   /* size of memory in controller */
 32      interlace fixed bin (3);                               /* memory interlace type */
 33 
 34 dcl  rsw_1_3_data bit (36) aligned,
 35      rsw_2_data bit (36) aligned,
 36      rsw_4_data bit (36) aligned,
 37     (rsw2p, rsw4p) ptr,
 38      rsw fixed bin (3);
 39 
 40 dcl  privileged_mode_ut$rsw entry (fixed bin (3), bit (36) aligned);
 41 
 42 dcl (addr, bin, divide) builtin;
 43 
 44 dcl  pip ptr;                                               /* pointer to port info */
 45 
 46 dcl 1 pi like rsw_1_3.port_info based (pip) unal;           /* port info */
 47 ^L
 48 % include rsw;
 49 ^L
 50 % include scs;
 51 
 52 ^L
 53 
 54 port_info: entry (tag, enabled, base, size, interlace);     /* entry to return info about a port */
 55 
 56 
 57           rsw2p = addr (rsw_2_data);                        /* Set pointer. */
 58           rswp = addr (rsw_1_3_data);                       /* Set pointer. */
 59           call privileged_mode_ut$rsw (2, rsw_2_data);      /* get the cpu type. */
 60           if rsw2p -> dps8_rsw_2.cpu_type = 1 then do;      /* if DPS8 cpu... */
 61                if tag > 3 then do;                          /*  can't have for than 4 scus on dps8 so... */
 62                     enabled = "0"b;                         /* tell caller this port disabled */
 63                     return;
 64                end;
 65                pip = addr (rsw_1_3.port_info (tag));        /* there can only be 4 SCUs... */
 66                call privileged_mode_ut$rsw (1, rsw_1_3_data); /* Read port info. */
 67                size = divide (dps8_mem_size_table (pi.mem_size), 1024, 17, 0);
 68                base = bin (pi.port_assignment, 3) * size;   /* Compute base address of memory. */
 69                if pi.interlace_enable then                  /* If interlace is enabled ... */
 70                     if rsw2p -> dps8_rsw_2.interlace_info (tag) then /* If two-word interlace... */
 71                          interlace = 2;
 72                     else interlace = 4;                     /* If four-word interlace ... */
 73                else interlace = 0;                          /* If no interlace ... */
 74           end;
 75           else do;                                          /* must be a DPS or L68 cpu */
 76                rsw4p = addr (rsw_4_data);                   /* Set pointer to data. */
 77                if tag < 4 then do;                          /* Decide on RSW 1 or RSW 3 data. */
 78                     rsw = 1;
 79                     pip = addr (rsw_1_3.port_info (tag));
 80                end;
 81                else do;
 82                     rsw = 3;
 83                     pip = addr (rsw_1_3.port_info (tag - 4));
 84                end;
 85                call privileged_mode_ut$rsw (rsw, rsw_1_3_data); /* Read port info. */
 86                call privileged_mode_ut$rsw (4, rsw_4_data); /* Read half/full and interlace type data. */
 87                size = divide (dps_mem_size_table (pi.mem_size), 1024, 17, 0);
 88                base = bin (pi.port_assignment, 3) * size;   /* Compute base address of memory. */
 89                if rsw4p -> rsw_4.half (tag) then
 90                     size = divide (size, 2, 17, 0);         /* Halve the size if so indicated. */
 91                if pi.interlace_enable then                  /* If interlace is enabled ... */
 92                     if rsw4p -> rsw_4.four (tag) then       /* If two-word interlace ... */
 93                          interlace = 2;
 94                     else interlace = 4;                     /* If four-word interlace ... */
 95                else interlace = 0;                          /* If no interlace ... */
 96           end;
 97           enabled = pi.port_enable;                         /* Return port enabled bit. */
 98 
 99           return;
100 ^L
101 
102 set_rsw_mask: entry (tag, enabled);                         /* entry to set mask for checking CPU switches */
103 
104 
105           if tag < 4 then do;                               /* Set appropriate RSW data. */
106                rswp = addr (scs$processor_switch_mask (1));
107                pip = addr (rsw_1_3.port_info (tag));
108           end;
109           else do;
110                rswp = addr (scs$processor_switch_mask (3));
111                pip = addr (rsw_1_3.port_info (tag - 4));
112           end;
113 
114           pi.port_enable = enabled;                         /* Set or clear enabled bit. */
115 
116           return;
117 
118 
119 
120 init_rsw_mask: entry (tag, enabled);                        /* entry to set initial mask for switch checking */
121 
122 
123           if tag < 4 then do;                               /* Set appropriate RSW data. */
124                rswp = addr (scs$processor_switch_mask (1));
125                pip = addr (rsw_1_3.port_info (tag));
126           end;
127           else do;
128                rswp = addr (scs$processor_switch_mask (3));
129                pip = addr (rsw_1_3.port_info (tag - 4));
130           end;
131 
132           pi.port_assignment = "111"b;                      /* Compare port assignment switches. */
133           pi.interlace_enable = "1"b;                       /* Compare interlace enable switches. */
134           pi.mem_size = 7;                                  /* Compare mem size switches. */
135           pi.port_enable = enabled;                         /* Compare enable switch only if enabled. */
136 
137           rswp = addr (scs$processor_switch_mask (4));
138           rsw_4.four (tag) = "1"b;                          /* Compare four-word interlace switches. */
139           rsw_4.half (tag) = "1"b;                          /* Compare half/full switches. */
140 
141           if tag < 4 then do;                               /* Set appropriate RSW data. */
142                rswp = addr (scs$processor_switch_template (1));
143                pip = addr (rsw_1_3.port_info (tag));
144           end;
145           else do;
146                rswp = addr (scs$processor_switch_template (3));
147                pip = addr (rsw_1_3.port_info (tag - 4));
148           end;
149 
150           pi.port_enable = "1"b;                            /* If compared, this bit must be ON. */
151 
152           return;
153 
154 
155 
156      end rsw_util;