1 /* BEGIN INCLUDE FILE scs.incl.pl1 ... March 1983 */
  2 /* format: style4 */
  3 
  4 /* Information about system controllers */
  5 
  6 dcl  1 scs$controller_data (0:7) aligned ext,               /* per-controller info */
  7        2 size fixed bin (17) unaligned,                     /* size (in 1024 word blocks) of this controller */
  8        2 base fixed bin (17) unaligned,                     /* abs address (0 mod 1024) for base of this controller */
  9        2 eima_data (4) unaligned,                           /* EIMA information for this controller */
 10          3 mask_available bit (1) unaligned,                /* ON if corresponding mask exists */
 11          3 mask_assigned bit (1) unaligned,                 /* ON if mask assigned to a port */
 12          3 mbz bit (3) unaligned,
 13          3 mask_assignment fixed bin (3) unaligned,         /* port to which mask is assigned */
 14        2 info aligned,
 15          3 online bit (1) unaligned,                        /* ON if controller is online */
 16          3 offline bit (1) unaligned,                       /* ON if controller is offline but can be added */
 17          3 store_a_online bit (1) unaligned,                /* ON if store A is online */
 18          3 store_a1_online bit (1) unaligned,               /* ON if store A1 is online */
 19          3 store_b_online bit (1) unaligned,                /* ON if store B is online */
 20          3 store_b1_online bit (1) unaligned,               /* ON if store B1 is online */
 21          3 store_b_is_lower bit (1) unaligned,              /* ON if store B is lower */
 22          3 ext_interlaced bit (1) unaligned,                /* ON if this SCU is interlaced with other SCU */
 23          3 int_interlaced bit (1) unaligned,                /* ON if this SCU is internally interlaced */
 24          3 four_word bit (1) unaligned,                     /* ON if external interlace is 4-word */
 25          3 cyclic_priority (7) bit (1) unaligned,           /* Cyclic priority for adjacent ports */
 26          3 type bit (4) unaligned,                          /* Model number for this controller */
 27          3 abs_wired bit (1) unaligned,                     /* ON if controller can have abs_wired pages */
 28          3 program bit (1) unaligned,                       /* PROGRAM/MANUAL switch setting */
 29          3 mbz bit (13) unaligned,
 30        2 lower_store_size fixed bin (17) unaligned,         /* size (in 1024 word blocks) of lower store */
 31        2 upper_store_size fixed bin (17) unaligned;         /* size (in 1024 word blocks) of upper store */
 32 
 33 /* Information about CPUs */
 34 
 35 dcl  1 scs$processor_data (0:7) aligned ext,                /* information about CPUs in the system */
 36        (
 37        2 online bit (1),                                    /* "1"b if CPU is online */
 38        2 offline bit (1),                                   /* "1"b if CPU is offline but can be added */
 39        2 release_mask bit (1),                              /* "1"b is this CPU is to give up its mask */
 40        2 accept_mask bit (1),                               /* "1"b if this CPU is to grap mask in idle loop */
 41        2 delete_cpu bit (1),                                /* "1"b if this CPU is to delete itself */
 42        2 interrupt_cpu bit (1),                             /* "1"b if this CPU takes hardware interrupts */
 43        2 halted_cpu bit (1),                                /* "1"b if this CPU has stopped itself (going to BOS) */
 44        2 cpu_type fixed bin (2) unsigned,                   /*  0 => DPS or L68, 1 => DPS8 */
 45        2 mbz1 bit (6),
 46        2 cache_size fixed bin (3) unsigned,                 /* 0 = No cache; 1 = L68 2K cache;
 47                                                                2 = DPS8 8K cache; 3 = DPS8 VS&SC 8K cache;
 48                                                                4 = DPS8 VS&SC 16K cache; 5 = DPS8 VS&SC 32K cache
 49                                                                7 = ignore cache size (set by ISOLTS reconfig) */
 50        2 mbz2 bit (12),
 51        2 expanded_port bit (1),                             /* "1"b = on expanded port */
 52        2 expander_port fixed bin (2) unsigned,              /* The actual expander port */
 53        2 controller_port fixed bin (3) unsigned
 54        ) unaligned;                                         /* Port on controller */
 55 
 56 dcl  1 scs$port_data (0:7) aligned external static,         /* Info about what is connected to each SCU port */
 57        2 assigned fixed bin (4) unsigned unaligned,         /* Type of device on this port                    */
 58        2 expander_port bit (1) unaligned,                   /* "1"b => this port has a port expander */
 59        2 expanded_cpu (0:3) bit (1) unaligned,              /* "1"b => this expander port has a CPU attached */
 60        2 iom_number fixed bin (3) unsigned unaligned,       /* IOM number of IOM attached to this port */
 61        2 cpu_number (0:3) fixed bin (3) unsigned unaligned, /* CPU number of CPU(s) attached to this port */
 62                                                             /* cpu_number (0) is only one if expander_port is "0"b */
 63        2 pad bit (12) unaligned;
 64 
 65 dcl  1 scs$cow (0:7) aligned external,                      /* Actual connect words */
 66        2 pad bit (36) aligned,                              /* Expander COW's must be odd-word */
 67        2 cow,
 68          3 sub_mask bit (8) unaligned,                      /* Expander sub-port mask */
 69          3 mbz1 bit (13) unaligned,
 70          3 expander_command bit (3) unaligned,              /* Expander command. */
 71          3 mbz2 bit (2) unaligned,
 72          3 expanded_port bit (1) unaligned,                 /* "1"b = on expanded port */
 73          3 expander_port fixed bin (3) unsigned unaligned,  /* Port on expander for cioc */
 74          3 mbz3 bit (3) unaligned,
 75          3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
 76 
 77 dcl  1 scs$cow_ptrs (0:7) external aligned,                 /* Pointers to COW's */
 78        2 rel_cow_ptr bit (18) unal,                         /* Relative pointer to COW */
 79        2 pad bit (12) unal,
 80        2 tag bit (6) unal;                                  /* Better be zero. */
 81 
 82 dcl  1 scs$reconfig_general_cow aligned external,           /* Used during reconfig ops. */
 83        2 pad bit (36) aligned,
 84        2 cow,                                               /* Connect operand word, in odd location. */
 85          3 sub_mask bit (8) unaligned,                      /* Expander sub-port mask */
 86          3 mbz1 bit (13) unaligned,
 87          3 expander_command bit (3) unaligned,              /* Expander command. */
 88          3 mbz2 bit (9) unaligned,
 89          3 controller_port fixed bin (3) unaligned unsigned;/* controller port for this CPU */
 90 
 91 /* MASKS and PATTERNS */
 92 
 93 dcl  scs$sys_level bit (72) aligned ext;                    /* mask used while handling I/O interrupts */
 94 dcl  scs$open_level bit (72) aligned ext;                   /* mask used during normal operation */
 95 dcl  scs$processor_start_mask bit (72) aligned ext;         /* mask used when starting up a CPU */
 96 dcl  scs$cpu_test_mask bit (72) aligned ext;                /* mask used for ISOLTS CPU testing */
 97 dcl  scs$number_of_masks fixed bin ext;                     /* number of masks (starting at sys_level) */
 98 dcl  scs$processor_start_pattern bit (36) aligned ext;      /* SMIC pattern used to send processor start interrupt */
 99 dcl  scs$cpu_test_pattern bit (36) aligned ext;             /* SMIC pattern used for ISOLTS processor testing */
100 
101 /* CAM and CACHE clear info */
102 
103 dcl  scs$cam_pair fixed bin (71) ext;                       /* instructions XEDd when CAMing and clearing CACHE */
104 dcl  scs$cam_wait bit (8) aligned ext;                      /* Used when evicting pages from main memory */
105 
106 /* MASKING INSTRUCTIONS & POINTERS */
107 
108 dcl  scs$set_mask (0:7) bit (36) aligned ext;               /* instructions to set mask (STAQ or SMCM) */
109 dcl  scs$read_mask (0:7) bit (36) aligned ext;              /* instructions to read mask (LDAQ or RMCM) */
110 dcl  scs$mask_ptr (0:7) ptr unaligned ext;                  /* pointers for real or simulated masks */
111 
112 /* MISCELLANEOUS */
113 
114 dcl  1 scs$processor_test_data aligned ext,                 /* info used for cpu testing */
115        (
116        2 active bit (1),                                    /* = "1"b if cpu currently under test */
117        2 scu_state bit (2),                                 /* state of scu being used for testing (see definition below) */
118        2 pad1 bit (4),
119        2 req_mem fixed bin (10),                            /* dedicated memory required to test this cpu */
120        2 cpu_tag fixed bin (5),                             /* tag of cpu under test */
121        2 scu_tag fixed bin (5),                             /* tag of scu being used for cpu testing */
122        2 mask_cpu fixed bin (5)
123        ) unaligned;                                         /* tag of active cpu that has mask asigned to above scu */
124 
125 /* scu_state = "00"b => SCU defined by scs$processor_test_data.scu_tag not yet effected */
126 /* scu_state = "01"b => all core removed from SCU, port mask not yet changed */
127 /* scu_state = "10"b => all core removed from SCU, port mask changed */
128 /* scu_state = "11"b => only 64k at base of SCU being used for testing, original port mask restored */
129 
130 dcl  scs$idle_aptep (0:7) ptr unaligned ext;                /* pointer to idle process APTE for each processor */
131 
132 dcl  scs$connect_lock bit (36) aligned ext;                 /* lock for sending connects */
133 dcl  scs$reconfig_lock bit (36) aligned ext;                /* Lock used during reconfiguration */
134 dcl  scs$trouble_flags bit (8) aligned ext;                 /* checkoff flags for sys_trouble stopping */
135 dcl  scs$bos_restart_flags bit (8) aligned ext;             /* checkoff flags for restarting after sys_trouble */
136 dcl  scs$nprocessors fixed bin ext;                         /* number of runnung processors */
137 dcl  scs$bos_processor_tag fixed bin (3) ext;               /* CPU tag of processor running BOS */
138 dcl  scs$faults_initialized bit (1) aligned ext;            /* ON after faults have been enabled */
139 dcl  scs$sys_trouble_pending bit (1) aligned ext;           /* sys_trouble event is pending in the system */
140 dcl  scs$fast_cam_pending (0:7) bit (36) aligned ext;       /* checkoff cells for cam connect                 */
141 dcl  scs$interrupt_controller fixed bin (3) ext;            /* port number of low order controller */
142 dcl  scs$processor_start_int_no fixed bin (5) ext;          /* interrupt cell for starting a processor */
143 dcl  scs$processor bit (8) aligned ext;                     /* bits ON for online CPUs */
144 dcl  scs$processor_start_wait bit (8) aligned ext;          /* checkoff flags for waiting for new processor */
145 
146 dcl  scs$trouble_dbrs (0:7) fixed bin (71);                 /* DBR values at system crash time */
147 
148 dcl  scs$port_addressing_word (0:7) bit (3) aligned ext;    /* active module port number for each controller */
149 
150 dcl  scs$cfg_data (0:7) fixed bin (71) aligned ext;         /* RSCR-CFG data from each controller */
151 
152 dcl  scs$cfg_data_save fixed bin (71) aligned ext;          /* RSCR-CFG save area for ISOLTS CPU testing */
153 
154 dcl  scs$expanded_ports bit (1) unaligned dim (0:7) external;
155                                                             /* Which ports have expanders */
156 
157 dcl  scs$processor_switch_data (0:4) bit (36) aligned ext;  /* raw data from RSW 0 thru 4 */
158 dcl  scs$processor_switch_template (0:4) bit (36) aligned ext; /* expected data from RSW 0 thru 4 */
159 dcl  scs$processor_switch_compare (0:4) bit (36) aligned ext; /* discrepancies from expected data */
160 dcl  scs$processor_switch_mask (0:4) bit (36) aligned ext;  /* masks for comparing switch data */
161 
162 dcl  scs$processor_data_switch_value bit (36) aligned ext;  /* Correct value for CPU data switches */
163 
164 dcl  scs$controller_config_size (0:7) fixed bin (14) aligned ext;
165                                                             /* Controller size on config card */
166 
167 dcl  scs$reconfig_locker_id char (32) aligned ext;          /* process group ID of process doing reconfiguration */
168 
169 dcl  scs$scas_page_table (0:31) bit (36) aligned external static;
170                                                             /* PTWs for SCAS pages */
171 
172 dcl  scs$cycle_priority_template bit (7) aligned ext;       /* template for setting anti-hog switches         */
173 dcl  scs$set_cycle_switches bit (1) aligned ext;            /* flag to set ant-hog switches                   */
174 
175 
176 dcl  (
177      IOM_PORT init (1),
178      CPU_PORT init (2),
179      BULK_PORT init (3)
180      ) fixed bin int static options (constant);             /* values for scs$port_data.assigned              */
181 
182 
183 /* END INCLUDE FILE scs.incl.pl1 */