1 /* Begin include file ...... scr.incl.pl1 2 modified 5/75 by Noel I. Morris 3 modified 10/81 by M.R. Jordan for 64K chip, M64 memory 4 modified '83 to make values constant */ 5 6 /* This include file is to be used in conjunction with pmut$rscr and pmut$sscr. 7 Wherever possible the terms in the processor manual are used in the declaration. */ 8 9 dcl (SC_MR init (0), /* SC Mode Register */ 10 SC_CFG init (1), /* SC Configuration Switches */ 11 SC_MSK init (2), /* SC Interrupt Mask */ 12 SC_IC init (3), /* SC Interrupt Cells */ 13 SC_ETC init (4), /* SC Elapsed Time Clock */ 14 SC_SU init (6)) fixed bin (6) static options (constant); /* SU Mode Register */ 15 16 17 dcl scrp ptr; /* pointer to SC data */ 18 19 dcl 1 scr_cfg1 based (scrp) aligned, /* configuration data for 6000 SC */ 20 21 (2 mode_a bit (3), /* 000 => on-line 22 001 => test mode 23 010 => off-line */ 24 2 bdry_a bit (3), /* 000 => 32K, 001 => 64K, etc */ 25 2 mode_b bit (3), /* see mode_a */ 26 2 bdry_b bit (3), /* see bdry_a */ 27 2 int bit (1), /* 1 => stores are internally interlaced */ 28 2 lwr bit (1), /* 1 => store B is low */ 29 2 addr_offset bit (2), /* 00 => no offset, 01 => 32K offset, etc. */ 30 2 port_no bit (4), /* requester's port number */ 31 2 port_enable (0:7) bit (2), /* 00 => port disabled 32 01 => port under program control 33 11 => port enabled */ 34 2 pima (4) bit (9)) unaligned; /* program interrupt mask assignments 35 000 => unassigned 36 400 => assigned to port 0 37 200 => assigned to port 1 38 . 39 . 40 . 41 002 => assigned to port 7 42 001 => assigned to maint. panel */ 43 44 45 dcl 1 scr_cfg2 based (scrp) aligned, /* configuration data for 4MW SCU */ 46 47 (2 mask_a_assign bit (9), /* interrupt mask "A" port assignment 48 400 => assigned to port 0 49 . 50 . 51 002 => assigned to port 7 52 001 => mask off */ 53 2 size bit (3), /* size of lower store */ 54 2 a_online bit (1), /* 1 => store A online */ 55 2 a1_online bit (1), /* 1 => store A1 online */ 56 2 b_online bit (1), /* 1 => store B online */ 57 2 b1_online bit (1), /* 1 => store B1 online */ 58 2 port_no bit (4), /* requester's port number */ 59 2 pad1 bit (1), 60 2 mode bit (1), /* 1 => programmable mode */ 61 2 nea_enabled bit (1), /* 1 => non-existent address logic enabled */ 62 2 nea bit (7), /* 001 => 32K, 002 => 64K, 003 => 96K, etc. */ 63 2 int bit (1), /* 1 => stores are internally interlaced */ 64 2 lwr bit (1), /* 1 => store B is low */ 65 2 port_mask_0_3 bit (4), /* 1 => corresponding port enabled */ 66 67 2 mask_b_assign bit (9), /* interrupt mask "B" port assignment */ 68 2 pad2 bit (12), 69 2 cyclic_prior bit (7), /* cyclic port priority switches */ 70 2 pad3 bit (4), 71 2 port_mask_4_7 bit (4)) unal; /* 1 => corresponding port enabled */ 72 73 74 dcl 1 scr_mr based (scrp) aligned, /* SC mode register */ 75 76 (2 pad1 bit (50), 77 2 identification bit (4), /* 0000 => 8034, 8035 78 0001 => 6000 SC 79 0010 => 4MW SCU */ 80 2 TS_strobe_margin bit (2), /* 00 => normal timing 81 01 => slow timing 82 10 => inhibit strobe 83 11 => fast timing */ 84 2 G0_strobe_margin bit (2), 85 2 ANSWER_strobe_margin bit (2), 86 2 DA_strobe_margin bit (2), 87 2 EOC_strobe_margin bit (2), 88 2 PLUS_5_VOLT_margin bit (2), /* 00 => normal voltage 89 01 => -5% 90 10 => normal voltage 91 11 => +5% */ 92 2 parity_override bit (1), /* 1 => SU forced to accept data with incorrect parity */ 93 2 parity_disable bit (1), /* 1 => disable data and ZAC parity checking */ 94 2 store_IA_disable bit (1), /* 1 => disable illegal action indication */ 95 2 ZAC_parity_error bit (1), /* 1 => cause ZAC parity error */ 96 2 SGR_accepted bit (1), /* 1 => SGR command accepted by SC */ 97 2 pad2 bit (1)) unal; 98 99 100 dcl 1 scr_msk based (scrp) aligned, /* SC mask register */ 101 102 (2 interrupt_mask_1 bit (16), /* mask bits for interrupts 0 thru 15 */ 103 2 pad1 bit (16), 104 2 port_mask_1 bit (4), /* mask bits for ports 0 thru 3 */ 105 106 2 interrupt_mask_2 bit (16), /* mask bits for interrupts 16 thru 31 */ 107 2 pad2 bit (16), 108 2 port_mask_2 bit (4)) unal; /* mask bits for ports 4 thru 7 */ 109 110 111 dcl 1 scr_su based (scrp) aligned, /* store unit mode register */ 112 113 (2 pad1 bit (36), 114 2 ZAC_line bit (6), /* EDAC mode only - address field */ 115 2 syndrome bit (8), /* EDAC mode only - failure syndrome */ 116 2 identification bit (4), /* 0000 => High Speed Core Model AA1 117 0001 => High Speed Core Model AA3 118 0011 => 4K, 16 pin chip, MOS memory, M32 boards 119 0100 => 1K chip MOS memory with EDAC enabled 120 1010 => 64K, 16 pin chip, MOS memory, M64 boards 121 1011 => 16K, 16 pin chip, MOS memory, M264 boards 122 1100 => 1K chip MOS memory with EDAC disabled 123 1110 => 16K, 16 pin chip, MOS memory, M128 boards 124 1111 => 4K, 22 pin chip MOS memory, M16 boards */ 125 2 EDAC_disabled bit (1), /* 1 => correction disabled but detection still enabled */ 126 2 pad2 bit (4), 127 2 MINUS_5_VOLT_margin bit (2), 128 2 PLUS_5_VOLT_margin bit (2), 129 2 spare_margin bit (2), 130 2 PLUS_19_VOLT_margin bit (2), 131 2 pad3 bit (1), 132 2 SENSE_strobe_margin bit (2), /* core only */ 133 2 pad4 bit (1), 134 2 maint_functions_enabled bit (1)) unal; /* 1 => maintenance functions enabled */ 135 136 /* End of include file ...... scr.incl.pl1 */ 137