1 2 3 "BEGIN INCLUDE FILE scr.incl.alm 4 5 6 "Created 09/28/82 1727.1 edt Tue by convert_include_file, 7 " Version of 07/15/82 2204.3 edt Thu. 8 9 "Made from >ldd>include>scr.incl.pl1, 10 " modified 06/03/82 1518.6 edt Thu 11 12 13 equ SC_MR,0 " MANIFEST 14 equ SC_CFG,1 " MANIFEST 15 equ SC_MSK,2 " MANIFEST 16 equ SC_IC,3 " MANIFEST 17 equ SC_ETC,4 " MANIFEST 18 equ SC_SU,6 " MANIFEST 19 20 " 21 " Structure scr_cfg1 22 " 23 equ scr_cfg1_size,2 24 25 equ scr_cfg1.mode_a_word,0 26 equ scr_cfg1.mode_a_shift,33 27 bool scr_cfg1.mode_a_mask,000007 28 equ scr_cfg1.bdry_a_word,0 29 equ scr_cfg1.bdry_a_shift,30 30 bool scr_cfg1.bdry_a_mask,000007 31 equ scr_cfg1.mode_b_word,0 32 equ scr_cfg1.mode_b_shift,27 33 bool scr_cfg1.mode_b_mask,000007 34 equ scr_cfg1.bdry_b_word,0 35 equ scr_cfg1.bdry_b_shift,24 36 bool scr_cfg1.bdry_b_mask,000007 37 equ scr_cfg1.int_word,0 38 bool scr_cfg1.int,000040 " DU 39 equ scr_cfg1.lwr_word,0 40 bool scr_cfg1.lwr,000020 " DU 41 equ scr_cfg1.addr_offset_word,0 42 equ scr_cfg1.addr_offset_shift,20 43 bool scr_cfg1.addr_offset_mask,000003 44 equ scr_cfg1.port_no_word,0 45 equ scr_cfg1.port_no_shift,16 46 bool scr_cfg1.port_no_mask,000017 47 equ scr_cfg1.port_enable_word,0 48 equ scr_cfg1.port_enable_shift,14 49 bool scr_cfg1.port_enable_mask,000003 50 51 equ scr_cfg1.pima_word,1 52 equ scr_cfg1.pima_shift,27 53 bool scr_cfg1.pima_mask,000777 54 55 " 56 " Structure scr_cfg2 57 " 58 equ scr_cfg2_size,2 59 60 equ scr_cfg2.mask_a_assign_word,0 61 equ scr_cfg2.mask_a_assign_shift,27 62 bool scr_cfg2.mask_a_assign_mask,000777 63 equ scr_cfg2.size_word,0 64 equ scr_cfg2.size_shift,24 65 bool scr_cfg2.size_mask,000007 66 equ scr_cfg2.a_online_word,0 67 bool scr_cfg2.a_online,000040 " DU 68 equ scr_cfg2.a1_online_word,0 69 bool scr_cfg2.a1_online,000020 " DU 70 equ scr_cfg2.b_online_word,0 71 bool scr_cfg2.b_online,000010 " DU 72 equ scr_cfg2.b1_online_word,0 73 bool scr_cfg2.b1_online,000004 " DU 74 equ scr_cfg2.port_no_word,0 75 equ scr_cfg2.port_no_shift,16 76 bool scr_cfg2.port_no_mask,000017 77 equ scr_cfg2.mode_word,0 78 bool scr_cfg2.mode,040000 " DL 79 equ scr_cfg2.nea_enabled_word,0 80 bool scr_cfg2.nea_enabled,020000 " DL 81 equ scr_cfg2.nea_word,0 82 equ scr_cfg2.nea_shift,6 83 bool scr_cfg2.nea_mask,000177 84 equ scr_cfg2.int_word,0 85 bool scr_cfg2.int,000040 " DL 86 equ scr_cfg2.lwr_word,0 87 bool scr_cfg2.lwr,000020 " DL 88 equ scr_cfg2.port_mask_0_3_word,0 89 equ scr_cfg2.port_mask_0_3_shift,0 90 bool scr_cfg2.port_mask_0_3_mask,000017 91 92 equ scr_cfg2.mask_b_assign_word,1 93 equ scr_cfg2.mask_b_assign_shift,27 94 bool scr_cfg2.mask_b_assign_mask,000777 95 equ scr_cfg2.cyclic_prior_word,1 96 equ scr_cfg2.cyclic_prior_shift,8 97 bool scr_cfg2.cyclic_prior_mask,000177 98 equ scr_cfg2.port_mask_4_7_word,1 99 equ scr_cfg2.port_mask_4_7_shift,0 100 bool scr_cfg2.port_mask_4_7_mask,000017 101 102 " 103 " Structure scr_mr 104 " 105 equ scr_mr_size,2 106 107 108 equ scr_mr.identification_word,1 109 equ scr_mr.identification_shift,18 110 bool scr_mr.identification_mask,000017 111 equ scr_mr.TS_strobe_margin_word,1 112 equ scr_mr.TS_strobe_margin_shift,16 113 bool scr_mr.TS_strobe_margin_mask,000003 114 equ scr_mr.G0_strobe_margin_word,1 115 equ scr_mr.G0_strobe_margin_shift,14 116 bool scr_mr.G0_strobe_margin_mask,000003 117 " equ scr_mr.ANSWER_strobe_margin_word,1 118 " equ scr_mr.ANSWER_strobe_margin_shift,12 119 " bool scr_mr.ANSWER_strobe_margin_mask,000003 120 equ scr_mr.DA_strobe_margin_word,1 121 equ scr_mr.DA_strobe_margin_shift,10 122 bool scr_mr.DA_strobe_margin_mask,000003 123 equ scr_mr.EOC_strobe_margin_word,1 124 equ scr_mr.EOC_strobe_margin_shift,8 125 bool scr_mr.EOC_strobe_margin_mask,000003 126 equ scr_mr.PLUS_5_VOLT_margin_word,1 127 equ scr_mr.PLUS_5_VOLT_margin_shift,6 128 bool scr_mr.PLUS_5_VOLT_margin_mask,000003 129 equ scr_mr.parity_override_word,1 130 bool scr_mr.parity_override,000040 " DL 131 equ scr_mr.parity_disable_word,1 132 bool scr_mr.parity_disable,000020 " DL 133 equ scr_mr.store_IA_disable_word,1 134 bool scr_mr.store_IA_disable,000010 " DL 135 equ scr_mr.ZAC_parity_error_word,1 136 bool scr_mr.ZAC_parity_error,000004 " DL 137 equ scr_mr.SGR_accepted_word,1 138 bool scr_mr.SGR_accepted,000002 " DL 139 140 " 141 " Structure scr_msk 142 " 143 equ scr_msk_size,2 144 145 equ scr_msk.interrupt_mask_1_word,0 146 equ scr_msk.interrupt_mask_1_shift,20 147 bool scr_msk.interrupt_mask_1_mask,177777 148 equ scr_msk.port_mask_1_word,0 149 equ scr_msk.port_mask_1_shift,0 150 bool scr_msk.port_mask_1_mask,000017 151 152 equ scr_msk.interrupt_mask_2_word,1 153 equ scr_msk.interrupt_mask_2_shift,20 154 bool scr_msk.interrupt_mask_2_mask,177777 155 equ scr_msk.port_mask_2_word,1 156 equ scr_msk.port_mask_2_shift,0 157 bool scr_msk.port_mask_2_mask,000017 158 159 " 160 " Structure scr_su 161 " 162 equ scr_su_size,2 163 164 165 equ scr_su.ZAC_line_word,1 166 equ scr_su.ZAC_line_shift,30 167 bool scr_su.ZAC_line_mask,000077 168 equ scr_su.syndrome_word,1 169 equ scr_su.syndrome_shift,22 170 bool scr_su.syndrome_mask,000377 171 equ scr_su.identification_word,1 172 equ scr_su.identification_shift,18 173 bool scr_su.identification_mask,000017 174 equ scr_su.EDAC_disabled_word,1 175 bool scr_su.EDAC_disabled,400000 " DL 176 equ scr_su.MINUS_5_VOLT_margin_word,1 177 " equ scr_su.MINUS_5_VOLT_margin_shift,11 178 bool scr_su.MINUS_5_VOLT_margin_mask,000003 179 equ scr_su.PLUS_5_VOLT_margin_word,1 180 equ scr_su.PLUS_5_VOLT_margin_shift,9 181 bool scr_su.PLUS_5_VOLT_margin_mask,000003 182 equ scr_su.spare_margin_word,1 183 equ scr_su.spare_margin_shift,7 184 bool scr_su.spare_margin_mask,000003 185 equ scr_su.PLUS_19_VOLT_margin_word,1 186 " equ scr_su.PLUS_19_VOLT_margin_shift,5 187 bool scr_su.PLUS_19_VOLT_margin_mask,000003 188 equ scr_su.SENSE_strobe_margin_word,1 189 " equ scr_su.SENSE_strobe_margin_shift,2 190 bool scr_su.SENSE_strobe_margin_mask,000003 191 " equ scr_su.maint_functions_enabled_word,1 192 bool scr_su.maint_functions_enabled,000001 " DL 193 194 "END INCLUDE FILE scr.incl.alm