1 /* *********************************************************** 2 * * 3 * Copyright, (C) Honeywell Information Systems Inc., 1982 * 4 * * 5 *********************************************************** */ 6 /* Begin include file ...... rsw.incl.pl1 7 Modified 3/26/77 by Noel I. Morris 8 Modified 9/03/80 by J. A. Bush for the DPS8/70M CPU 9 Modified 3/24/82 by J. A. Bush to allow the L68 CPU to address 4MW/port */ 10 11 dcl rswp ptr; 12 13 dcl 1 dps_rsw_2 aligned based (rswp), /* rsw 2 template for DPS and L68 CPUs */ 14 (2 pad1 bit (4), 15 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 16 2 fault_base bit (7), /* high order bits of fault vector */ 17 2 pad2 bit (6), 18 2 dps_option bit (1), /* "1"b => DPS CPU, "0"b => L68 CPU */ 19 2 pad3 bit (7), 20 2 cache2 bit (1), /* "1"b => 2k cache installed, "0"b => no cache */ 21 2 ext_gcos bit (1), /* "1"b => ext gcos option installed */ 22 2 id bit (4), /* CPU ID - "1110"b => L68 */ 23 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ 24 25 dcl 1 dps8_rsw_2 aligned based (rswp), /* rsw 2 template for DPS8 CPUs */ 26 (2 interlace_info (0:3) bit (1), /* if interlace enabled; "0"b => 4-word, "1"b => 2-word */ 27 2 cpu_type fixed bin (2) unsigned, /* 0 = L68 or DPS, 1 = DPS8 */ 28 2 fault_base bit (7), /* high order bits of fault vector */ 29 2 id_prom bit (1), /* "1"b => id_prom present */ 30 2 pad1 bit (5), 31 2 dps_option bit (1), /* always "1"b for DPS8 CPU */ 32 2 cache8 bit (1), /* "1"b => 8k cache installed, "0"b => no cache */ 33 2 pad2 bit (2), 34 2 multics_cpu bit (1), /* always "1"b for Multics cpu */ 35 2 pad3 bit (5), 36 2 cpu_speed bit (4), /* cpu speed options */ 37 2 cpu_num fixed bin (3) unsigned) unaligned; /* processor number */ 38 39 dcl 1 rsw_1_3 aligned based (rswp), /* rsw 3 only valid on DPS and L68 CPUs */ 40 (2 port_info (0:3), /* controller port information */ 41 3 port_assignment bit (3), /* port address assignment */ 42 3 port_enable bit (1), /* "1"b => port enabled */ 43 3 initialize_enable bit (1), /* "1"b => system initialize enabled */ 44 3 interlace_enable bit (1), /* "1"b => port is interlaced with neighbor */ 45 3 mem_size fixed bin (3) unsigned) unaligned; /* encoded memory size on port */ 46 47 dcl 1 rsw_4 aligned based (rswp), /* rsw 4 only valid on DPS and L68 CPUs */ 48 (2 pad1 bit (13), 49 2 port_info (0:7), /* additional controller port information */ 50 3 four bit (1), /* "0"b => 4-word interlace - "1"b => 2-word interlace */ 51 3 half bit (1), /* "1"b => only half of memory on controller in use */ 52 2 pad2 bit (7)) unaligned; 53 54 dcl dps_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS and L68 memory sizes */ 55 (32768, 65536, 4194304, 131072, 524288, 1048576, 2097152, 262144); 56 57 /* Note that the third array element above, is changed incompatibly in MR10.0. 58 In previous releases, this array element was used to decode a port size of 59 98304 (96K). With MR10.0 it is now possible to address 4MW per CPU port, by 60 installing FCO # PHAF183 and using a group 10 patch plug, on L68 and DPS CPUs. 61 */ 62 63 dcl dps8_mem_size_table (0:7) fixed bin (24) static options (constant) init /* DPS8 memory sizes */ 64 (32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304); 65 66 dcl rsw_valid (0:1) fixed bin static options (constant) init (5, 3); /* # of rsw valid per cpu type */ 67 68 /* End of include file ...... rsw.incl.pl1 */