1 /*    BEGIN INCLUDE FILE ... mode_reg.incl.pl1 ... last modified 6/72 */
 2 
 3 dcl  mrp ptr;
 4 
 5 dcl 1 mrg based(mrp) aligned,
 6     (2 ffv bit(15),                                         /* floating fault vector address */
 7     2 pad0 bit(1),
 8     2 top bit(1),                                           /* trap on op code match */
 9     2 tam bit(1),                                           /* trap on address match */
10     2 opcss bit(10),                                        /* op code / software switches */
11     2 tcuov bit(1),                                         /* trap on CU overflow */
12     2 scuop bit(1),                                         /* strobe CU on opcode match */
13     2 ehr bit(1),                                           /* enable history regs */
14     2 ehrrs bit(1),                                         /* enable history regs reset */
15     2 pad1 bit(3),
16     2 emr bit(1)) unaligned;                                /* enable mode register */
17 dcl 1 mrg_sw based(mrp) aligned,
18     (2 pad0 bit(18),
19     2 scuolin bit(1),                                       /* set CU overlap inhibit */
20     2 ssolin bit(1),                                        /* set Store overlap inhibit */
21     2 ssdpar bit(1),                                        /* set Store incorrect data parity */
22     2 sszacpar bit(1),                                      /* set Store incorrect ZAC parity */
23     2 pad1 bit(1),
24     2 svm bit(2),                                           /* set voltage margins */
25     2 pad2 bit(1),
26     2 stm bit(1),                                           /* set timing marigns */
27     2 pad3 bit(9))unaligned;
28 
29 /*     END INCLUDE FILE ... mode_reg.incl.pl1 */