1 /* ^L */ 2 /* BEGIN INCLUDE FILE mc.incl.pl1 Created Dec 72 for 6180 - WSS. */ 3 /* Modified 06/07/76 by Greenberg for mc.resignal */ 4 /* Modified 07/07/76 by Morris for fault register data */ 5 /* Modified 08/28/80 by J. A. Bush for the DPS8/70M CVPU */ 6 /* Modified '82 to make values constant */ 7 8 /* words 0-15 pointer registers */ 9 10 dcl mcp ptr; 11 12 dcl 1 mc based (mcp) aligned, 13 2 prs (0:7) ptr, /* POINTER REGISTERS */ 14 (2 regs, /* registers */ 15 3 x (0:7) bit (18), /* index registers */ 16 3 a bit (36), /* accumulator */ 17 3 q bit (36), /* q-register */ 18 3 e bit (8), /* exponent */ 19 3 pad1 bit (28), 20 3 t bit (27), /* timer register */ 21 3 pad2 bit (6), 22 3 ralr bit (3), /* ring alarm register */ 23 24 2 scu (0:7) bit (36), 25 26 2 mask bit (72), /* mem controller mask at time of fault */ 27 2 ips_temp bit (36), /* Temporary storage for IPS info */ 28 2 errcode fixed bin (35), /* fault handler's error code */ 29 2 fim_temp, 30 3 unique_index bit (18) unal, /* unique index for restarting faults */ 31 3 resignal bit (1) unal, /* recompute signal name with fcode below */ 32 3 fcode bit (17) unal, /* fault code used as index to FIM table and SCT */ 33 2 fault_reg bit (36), /* fault register */ 34 2 pad2 bit (1), 35 2 cpu_type fixed bin (2) unsigned, /* L68 = 0, DPS8/70M = 1 */ 36 2 ext_fault_reg bit (15), /* extended fault reg for DPS8/70M CPU */ 37 2 fault_time bit (54), /* time of fault */ 38 39 2 eis_info (0:7) bit (36)) unaligned; 40 41 42 dcl (apx fixed bin init (0), 43 abx fixed bin init (1), 44 bpx fixed bin init (2), 45 bbx fixed bin init (3), 46 lpx fixed bin init (4), 47 lbx fixed bin init (5), 48 spx fixed bin init (6), 49 sbx fixed bin init (7)) internal static options (constant); 50 51 52 ^L 53 54 dcl scup ptr; 55 56 dcl 1 scu based (scup) aligned, /* SCU DATA */ 57 58 59 /* WORD (0) */ 60 61 (2 ppr, /* PROCEDURE POINTER REGISTER */ 62 3 prr bit (3), /* procedure ring register */ 63 3 psr bit (15), /* procedure segment register */ 64 3 p bit (1), /* procedure privileged bit */ 65 66 2 apu, /* APPENDING UNIT STATUS */ 67 3 xsf bit (1), /* ext seg flag - IT modification */ 68 3 sdwm bit (1), /* match in SDW Ass. Mem. */ 69 3 sd_on bit (1), /* SDW Ass. Mem. ON */ 70 3 ptwm bit (1), /* match in PTW Ass. Mem. */ 71 3 pt_on bit (1), /* PTW Ass. Mem. ON */ 72 3 pi_ap bit (1), /* Instr Fetch or Append cycle */ 73 3 dsptw bit (1), /* Fetch of DSPTW */ 74 3 sdwnp bit (1), /* Fetch of SDW non paged */ 75 3 sdwp bit (1), /* Fetch of SDW paged */ 76 3 ptw bit (1), /* Fetch of PTW */ 77 3 ptw2 bit (1), /* Fetch of pre-paged PTW */ 78 3 fap bit (1), /* Fetch of final address paged */ 79 3 fanp bit (1), /* Fetch of final address non-paged */ 80 3 fabs bit (1), /* Fetch of final address absolute */ 81 82 2 fault_cntr bit (3), /* number of retrys of EIS instructions */ 83 84 85 /* WORD (1) */ 86 87 2 fd, /* FAULT DATA */ 88 3 iro bit (1), /* illegal ring order */ 89 3 oeb bit (1), /* out of execute bracket */ 90 3 e_off bit (1), /* no execute */ 91 3 orb bit (1), /* out of read bracket */ 92 3 r_off bit (1), /* no read */ 93 3 owb bit (1), /* out of write bracket */ 94 3 w_off bit (1), /* no write */ 95 3 no_ga bit (1), /* not a gate */ 96 3 ocb bit (1), /* out of call bracket */ 97 3 ocall bit (1), /* outward call */ 98 3 boc bit (1), /* bad outward call */ 99 3 inret bit (1), /* inward return */ 100 3 crt bit (1), /* cross ring transfer */ 101 3 ralr bit (1), /* ring alarm register */ 102 3 am_er bit (1), /* associative memory fault */ 103 3 oosb bit (1), /* out of segment bounds */ 104 3 paru bit (1), /* processor parity upper */ 105 3 parl bit (1), /* processor parity lower */ 106 3 onc_1 bit (1), /* op not complete type 1 */ 107 3 onc_2 bit (1), /* op not complete type 2 */ 108 109 2 port_stat, /* PORT STATUS */ 110 3 ial bit (4), /* illegal action lines */ 111 3 iac bit (3), /* illegal action channel */ 112 3 con_chan bit (3), /* connect channel */ 113 114 2 fi_num bit (5), /* (fault/interrupt) number */ 115 2 fi_flag bit (1), /* 1 => fault, 0 => interrupt */ 116 117 118 /* WORD (2) */ 119 120 2 tpr, /* TEMPORARY POINTER REGISTER */ 121 3 trr bit (3), /* temporary ring register */ 122 3 tsr bit (15), /* temporary segment register */ 123 124 2 pad2 bit (9), 125 126 2 cpu_no bit (3), /* CPU number */ 127 128 2 delta bit (6), /* tally modification DELTA */ 129 130 131 /* WORD (3) */ 132 133 2 word3 bit (18), 134 135 2 tsr_stat, /* TSR STATUS for 1,2,&3 word instructions */ 136 3 tsna, /* Word 1 status */ 137 4 prn bit (3), /* Word 1 PR number */ 138 4 prv bit (1), /* Word 1 PR valid bit */ 139 3 tsnb, /* Word 2 status */ 140 4 prn bit (3), /* Word 2 PR number */ 141 4 prv bit (1), /* Word 2 PR valid bit */ 142 3 tsnc, /* Word 3 status */ 143 4 prn bit (3), /* Word 3 PR number */ 144 4 prv bit (1), /* Word 3 PR valid bit */ 145 146 2 tpr_tbr bit (6), /* TPR.TBR field */ 147 148 149 /* WORD (4) */ 150 151 2 ilc bit (18), /* INSTRUCTION COUNTER */ 152 153 2 ir, /* INDICATOR REGISTERS */ 154 3 zero bit (1), /* zero indicator */ 155 3 neg bit (1), /* negative indicator */ 156 3 carry bit (1), /* carryry indicator */ 157 3 ovfl bit (1), /* overflow indicator */ 158 3 eovf bit (1), /* eponent overflow */ 159 3 eufl bit (1), /* exponent underflow */ 160 3 oflm bit (1), /* overflow mask */ 161 3 tro bit (1), /* tally runout */ 162 3 par bit (1), /* parity error */ 163 3 parm bit (1), /* parity mask */ 164 3 bm bit (1), /* ^bar mode */ 165 3 tru bit (1), /* truncation mode */ 166 3 mif bit (1), /* multi-word instruction mode */ 167 3 abs bit (1), /* absolute mode */ 168 3 hex bit (1), /* hexadecimal exponent mode */ 169 3 pad bit (3), 170 171 172 /* WORD (5) */ 173 174 2 ca bit (18), /* COMPUTED ADDRESS */ 175 176 2 cu, /* CONTROL UNIT STATUS */ 177 3 rf bit (1), /* on first cycle of repeat instr */ 178 3 rpt bit (1), /* repeat instruction */ 179 3 rd bit (1), /* repeat double instruction */ 180 3 rl bit (1), /* repeat link instruciton */ 181 3 pot bit (1), /* IT modification */ 182 3 pon bit (1), /* return type instruction */ 183 3 xde bit (1), /* XDE from Even location */ 184 3 xdo bit (1), /* XDE from Odd location */ 185 3 poa bit (1), /* operation preparation */ 186 3 rfi bit (1), /* tells CPU to refetch instruction */ 187 3 its bit (1), /* ITS modification */ 188 3 if bit (1), /* fault occured during instruction fetch */ 189 190 2 cpu_tag bit (6)) unaligned, /* computed tag field */ 191 192 193 /* WORDS (6,7) */ 194 195 2 even_inst bit (36), /* even instruction of faulting pair */ 196 197 2 odd_inst bit (36); /* odd instruction of faulting pair */ 198 199 200 201 202 203 204 /* ALTERNATE SCU DECLARATION */ 205 206 207 dcl 1 scux based (scup) aligned, 208 209 (2 pad0 bit (36), 210 211 2 fd, /* GROUP II FAULT DATA */ 212 3 isn bit (1), /* illegal segment number */ 213 3 ioc bit (1), /* illegal op code */ 214 3 ia_am bit (1), /* illegal address - modifier */ 215 3 isp bit (1), /* illegal slave procedure */ 216 3 ipr bit (1), /* illegal procedure */ 217 3 nea bit (1), /* non existent address */ 218 3 oobb bit (1), /* out of bounds */ 219 3 pad bit (29), 220 221 2 pad2 bit (36), 222 223 2 pad3a bit (18), 224 225 2 tsr_stat (0:2), /* TSR STATUS as an ARRAY */ 226 3 prn bit (3), /* PR number */ 227 3 prv bit (1), /* PR valid bit */ 228 229 2 pad3b bit (6)) unaligned, 230 231 2 pad45 (0:1) bit (36), 232 233 2 instr (0:1) bit (36); /* Instruction ARRAY */ 234 235 236 237 /* END INCLUDE FILE mc.incl.pl1 */