1 " BEGIN INCLUDE FILE mc.incl.alm 6/72 SHW
2 " Modified 8/80 by J. A. Bush for dps8/70M CPU
3 "
4 " HISTORY COMMENTS:
5 " 1) change2016-12-27Swenson, approve2016-12-25MCR10016,
6 " audit2016-12-27GDixon, install2016-12-27MR12.6f-0004:
7 " Fixed comment for scu.ir.mif indicator register.
8 " END HISTORY COMMENTS
9
10 " General layout of data items.
11
12 equ mc.prs,0 pointer registers
13 equ mc.regs,16 registers
14 equ mc.scu,24 SCU data
15 equ mc.eis_info,40 pointers and lengths for EIS
16
17 " Temporary storage for software
18
19 equ mc.mask,32 system controller mask at time of fault
20 equ mc.ips_temp,34 temporary storage for IPS info
21 equ mc.errcode,35 error code
22 equ mc.fim_temp,36 temporary to hold fault index and unique index
23 equ mc.fault_reg,37 fault register
24 equ mc.fault_time,38 time of fault
25 equ mc.cpu_type_word,38 CPU type from rsw 2. overlays part of time word
26 bool mc.cpu_type_mask,300000 DU
27 equ mc.ext_fault_reg,38 ext fault reg for dps8. overlays part of time word
28 bool mc.ext_fault_reg_mask,77774 DU
29 equ mc.cpu_type_shift,3 positions to shift right or left
30
31
32
33 " SCU DATA
34
35 " WORD 0 PROCEDURE POINTER REGISTER
36
37 equ mc.scu.ppr.prr_word,24 Procedure Ring Register
38 equ scu.ppr.prr_word,0
39 bool scu.ppr.prr_mask,700000 DU
40 equ scu.ppr.prr_shift,33
41
42 equ mc.scu.ppr.psr_word,24 Procedure Segment Register
43 equ scu.ppr.psr_word,0
44 bool scu.ppr.psr_mask,077777 DU
45 equ scu.ppr.psr_shift,18
46
47 equ mc.scu.ppr.p_word,24 Procedure Privileged Bit
48 equ scu.ppr.p_word,0
49 bool scu.ppr.p,400000 DL
50
51 " APPENDING UNIT STATUS
52 equ mc.scu.apu_stat_word,24 APPENDING UNIT STATUS
53 equ scu.apu_stat_word,0
54
55 bool scu.apu.xsf,200000 DL - Ext Seg Flag - IT mod.
56 bool scu.apu.sdwm,100000 DL - Match in SDW Ass. Mem.
57 bool scu.apu.sd_on,040000 DL - SDW Ass. Mem. ON
58 bool scu.apu.ptwm,020000 DL - Match in PTW Ass. Mem.
59 bool scu.apu.pt_on,010000 DL - PTW Ass. Mem. ON
60 bool scu.apu.pi_ap,004000 DL - Instr fetch or Append cycle
61 bool scu.apu.dsptw,002000 DL - Fetch of DSPTW
62 bool scu.apu.sdwnp,001000 DL - Fetch of SDW non-paged
63 bool scu.apu.sdwp,000400 DL - Fetch of SDW paged
64 bool scu.apu.ptw,000200 DL - Fetch of PTW
65 bool scu.apu.ptw2,000100 DL - Fetch of pre-paged PTW
66 bool scu.apu.fap,000040 DL - Fetch of final address paged
67 bool scu.apu.fanp,000020 DL - Fetch final address non-paged
68 bool scu.apu.fabs,000010 DL - Fetch of final address absolute
69
70 equ mc.scu.fault_cntr_word,24 Num of retrys of EIS instructions.
71 equ scu.fault_cntr_word,0
72
73 bool scu.fault_cntr_mask,000007
74
75
76 " WORD 1 FAULT DATA
77
78 equ mc.scu.fault_data_word,25 FAULT DATA
79 equ scu.fault_data_word,1
80
81 bool scu.fd.iro,400000 DU - Illegal Ring Order
82 bool scu.fd.oeb,200000 DU - Not In Execute Bracket
83 bool scu.fd.e_off,100000 DU - No Execute
84 bool scu.fd.orb,040000 DU - Not In Read Bracket
85 bool scu.fd.r_off,020000 DU - No Read
86 bool scu.fd.owb,010000 DU - Not In Write Bracket
87 bool scu.fd.w_off,004000 DU - No Write
88 bool scu.fd.no_ga,002000 DU - Not A Gate
89 bool scu.fd.ocb,001000 DU - Not in Call Bracket
90 bool scu.fd.ocall,000400 DU - Outward Call
91 bool scu.fd.boc,000200 DU - Bad Outward Call
92 bool scu.fd.inret,000100 DU - Inward Return
93 bool scu.fd.crt,000040 DU - Cross Ring Transfer
94 bool scu.fd.ralr,000020 DU - Ring Alarm
95 bool scu.fd.am_er,000010 DU - Assoc. Mem. Fault
96 bool scu.fd.oosb,000004 DU - Out Of Bounds
97 bool scu.fd.paru,000002 DU - Parity Upper
98 bool scu.fd.parl,000001 DU - Parity Lower
99
100 bool scu.fd.onc_1,400000 DL - Op Not Complete
101 bool scu.fd.onc_2,200000 DL - Op Not Complete
102
103 " GROUP II FAULT DATA
104 bool scu.fd.isn,400000 DU - Illegal Segment Number
105 bool scu.fd.ioc,200000 DU - Illegal Op Code
106 bool scu.fd.ia_im,100000 DU - Illegal Addr - Modifier
107 bool scu.fd.isp,040000 DU - Illegal Slave Procedure
108 bool scu.fd.ipr,020000 DU - Illegal Procedure
109 bool scu.fd.nea,010000 DU - Non Existent Address
110 bool scu.fd.oobb,004000 DU - Out Of Bounds
111
112 equ mc.scu.port_stat_word,25 PORT STATUS
113 equ scu.port_stat_word,1
114
115 bool scu.ial_mask,170000 DL - Illegal Action Lines
116 equ scu.ial_shift,12
117
118 bool scu.iac_mask,007000 DL - Illegal Action Channel
119 equ scu.iac_shift,9
120
121 bool scu.con_chan_mask,000700 DL - Connect Channel
122 equ scu.con_chan_shift,6
123
124 bool scu.fi_num_mask,000076 DL - Fault / Interrupt Number
125 equ scu.fi_num_shift,1
126
127 bool scu.fi_flag_mask,000001 DL - Fault / Interrupt Flag
128
129
130 " WORD 2 TEMPORARY POINTER REGISTER
131
132 equ mc.scu.tpr.trr_word,26 Temporary Ring Register
133 equ scu.tpr.trr_word,2
134 bool scu.tpr.trr_mask,700000 DU
135 equ scu.tpr.trr_shift,33
136
137 equ mc.scu.tpr.tsr_word,26 Temporary Segment Register
138 equ scu.tpr.tsr_word,2
139 bool scu.tpr.tsr_mask,077777 DU
140 equ scu.tpr.tsr_shift,18
141
142 equ mc.scu.cpu_no_word,26 CPU Number
143 equ scu.cpu_no_word,2
144
145 bool scu.cpu_no_mask,000700 DL
146 equ scu.cpu_shift,6
147
148 equ mc.scu.delta_word,26 Tally Modification DELTA
149 equ scu.delta_word,2
150
151 bool scu.delta_mask,000077 DL
152
153
154 " WORD 3 TSR STATUS
155
156 equ mc.scu.tsr_stat_word,27 TSR STATUS for 1,2, and 3
157 equ scu.tsr_stat_word,3 Word Instructions
158
159 bool scu.tsr_stat_mask,777700 DL - All of Status
160 equ scu.tsr_stat_shift,6
161
162 bool scu.tsna_mask,740000 DL - Word 1 Status
163 bool scu.tsna.prn_mask,700000 DL - Word 1 PR num
164 equ scu.tsna.prn_shift,15
165 bool scu.tsna.prv,040000 DL - Word 1 PR valid bit
166
167 bool scu.tsnb_mask,036000 DL - Word 2 Status
168 bool scu.tsnb.prn_mask,034000 DL - Word 2 PR num
169 equ scu.tsnb.prn_shift,11
170 bool scu.tsnb.prv,002000 DL - Word 2 PR valid bit
171
172 bool scu.tsnc_mask,0013 DL - Word 3 Status
173 bool scu.tsnc.prn_mask,001600 DL - Word 3 PR num
174 equ scu.tsnc.prn_shift,7
175 bool scu.tsnc.prv,000100 DL - Word 3 PR valid bit
176
177
178 equ mc.scu.tpr.tbr_word,27 TPR.TBR Field
179 equ scu.tpr.tbr_word,3
180
181 bool scu.tpr.tbr_mask,000077 DL
182
183
184 " WORD 4 INSTRUCTION COUNTER
185
186 equ mc.scu.ilc_word,28 INSTRUCTION COUNTER
187 equ scu.ilc_word,4
188 equ scu.ilc_shift,18
189
190 equ mc.scu.indicators_word,28 INDICATOR REGISTERS
191 equ scu.indicators_word,4
192
193 bool scu.ir.zero,400000 DL - Zero Indicator
194 bool scu.ir.neg,200000 DL - Negative Indicator
195 bool scu.ir.carry,100000 DL - Carry Indicator
196 bool scu.ir.ovfl,040000 DL - Overflow Indicator
197 bool scu.ir.eovf,020000 DL - Exponent Overflow Ind
198 bool scu.ir.eufl,010000 DL - Exponent Underflow Ind
199 bool scu.ir.oflm,004000 DL - Overflow Mask Indicator
200 bool scu.ir.tro,002000 DL - Tally Runout Indicator
201 bool scu.ir.par,001000 DL - Parity Indicator
202 bool scu.ir.parm,000400 DL - Parity Mask Indicator
203 bool scu.ir.bm,000200 DL - Bar Mode Indicator
204 bool scu.ir.tru,000100 DL - Truncation Indicator
205 bool scu.ir.mif,000040 DL - Mid-Instruction Fault Indicator
206 bool scu.ir.abs,000020 DL - Absolute Indicator
207 bool scu.ir.hex,000010 DL - Hexadecimal Indicator
208
209 " WORD 5 COMPUTED ADDRESS
210
211 equ mc.scu.ca_word,29 COMPUTED ADDRESS
212 equ scu.ca_word,5
213 equ scu.ca_shift,18
214
215 equ mc.scu.cu_stat_word,29 CONTROL UNIT STATUS
216 equ scu.cu_stat_word,5
217
218 bool scu.cu.rf,400000 DL - Repeat First
219 " On First Cycle of Repeat Inst.
220 bool scu.cu.rpt,200000 DL - Repeat Instruction
221 bool scu.cu.rd,100000 DL - Repeat Double Instr.
222 bool scu.cu.rl,040000 DL - Repeat Link Instr.
223
224 bool scu.cu.pot,020000 DL - IT Modification
225 bool scu.cu.pon,010000 DL - Return Type Instruction
226
227 bool scu.cu.xde,004000 DL - XDE from Even Location
228 bool scu.cu.xdo,002000 DL - XDE from Odd Location
229
230 bool scu.cu.poa,001000 DL - Operand Preparation
231 bool scu.cu.rfi,000400 DL - Tells CPU to refetch instruction
232 " This Bit Not Used 000200
233 bool scu.cu.if,000100 DL - Fault occurred during instruction fetch
234
235 equ mc.scu.cpu_tag_word,29 Computed Tag Field
236 equ scu.cpu_tag_word,5
237
238 bool scu.cpu_tag_mask,000007 DL
239
240
241 " WORDS 67 INSTRUCTIONS
242
243 equ scu.even_inst_word,30 Even Instruction
244
245 equ scu.odd_inst_word,31 Odd Instruction
246
247
248 " END INCLUDE FILE incl.alm