1 /* BEGIN INCLUDE FILE ... history_regs_l68.incl.pl1 ... last modified 10/80 */ 2 3 4 dcl (ouhrp, cuhrp, aphrp, duhrp, hr_data_ptr) ptr; 5 6 7 dcl ou_offset fixed bin init (0), /* offsets to hr data within the hr data block */ 8 cu_offset fixed bin init (32), 9 du_offset fixed bin init (64), 10 au_offset fixed bin init (96); 11 12 13 dcl 1 cuhra (16) based (cuhrp) aligned, 14 (2 pia bit (1), /* preparing instruction address */ 15 2 poa bit (1), /* preparing operand address */ 16 2 riw bit (1), /* requesting indirect word */ 17 2 siw bit (1), /* restoring indirect word */ 18 2 pot bit (1), /* preparing operand tally */ 19 2 pon bit (1), /* preparing operand address */ 20 2 raw bit (1), /* requesting alter-rewrite word */ 21 2 saw bit (1), /* restoring alter-rewrite word */ 22 2 trgo bit (1), /* transfer go - condition met */ 23 2 xde bit (1), /* XED from even location */ 24 2 xdo bit (1), /* XED from odd location */ 25 2 ic bit (1), /* even/odd inst. pair */ 26 2 rpts bit (1), /* repeat operation */ 27 2 wi bit (1), /* wait for instruction fetch */ 28 2 ar bit (1), /* address reg valid */ 29 2 nxip bit (1), /* not an xip address */ 30 2 nflt bit (1), /* not an FLT address */ 31 2 np bit (1), /* not in privilaged mode */ 32 2 op_code bit (10), /* op code of inst */ 33 2 inhib bit (1), /* inhibit int bit */ 34 2 its_flag bit (1), /* ar reg mod flag */ 35 2 tag bit (6), /* tag field of instr */ 36 2 ca_value bit (18), /* address field of inst */ 37 2 pcmd bit (5), /* processor command register */ 38 2 psl bit (4), /* port select lines */ 39 2 xint bit (1), /* execute interrupt */ 40 2 ins_fetch bit (1), /* inst fetch */ 41 2 cus bit (1), /* control unit store */ 42 2 ous bit (1), /* operations unit store */ 43 2 cul bit (1), /* control unit load */ 44 2 oul bit (1), /* operations unit load */ 45 2 dir bit (1), /* direct cycle */ 46 2 npcb bit (1), /* port logic not busy */ 47 2 pib bit (1)) unaligned; /* port interface busy */ 48 49 50 dcl 1 ouhra (16) based (ouhrp) aligned, 51 (2 nopc bit (9), /* next inst. op code */ 52 2 itw bit (1), /* IT tally word 6/9 bit data */ 53 2 ntg bit (3), /* next inst tag field */ 54 2 cmod bit (1), /* character modification */ 55 2 dir bit (1), /* direct modification */ 56 2 efad bit (2), /* LREG/SREG effective addr */ 57 2 pad0 bit (1), 58 2 rp bit (9), /* copy of RP reg */ 59 2 opbf bit (1), /* OU op code buffer full */ 60 2 frpf bit (1), /* primary register full */ 61 2 srf bit (1), /* secondary register full */ 62 2 gin bit (1), /* first cycle for all OU */ 63 2 gos bit (1), /* second cycle for OU - multiple OP */ 64 2 gd1 bit (1), /* first divide cycle */ 65 2 gd2 bit (1), /* second divide cycle */ 66 2 goe bit (1), /* exponent compare cycle */ 67 2 goa bit (1), /* mamtissa alignment cycle */ 68 2 gom bit (1), /* general OU cycle */ 69 2 gon bit (1), /* normalize cycle */ 70 2 gof bit (1), /* final cycle */ 71 2 fstr bit (1), /* OU store data available */ 72 2 dn bit (1), /* data not available */ 73 2 an bit (1), /* A reg not in use */ 74 2 qn bit (1), /* Q reg not used */ 75 2 x0n bit (1), /* X0 not in use */ 76 2 x1n bit (1), /* X1 not in use */ 77 2 x2n bit (1), /* X2 not in use */ 78 2 x3n bit (1), /* X3 not in use */ 79 2 x4n bit (1), /* X4 not in use */ 80 2 x5n bit (1), /* X5 not in use */ 81 2 x6n bit (1), /* X6 not in use */ 82 2 x7n bit (1), /* X7 not in use */ 83 2 pad1 bit (3), 84 2 ict bit (18)) unaligned; /* address of OU inst */ 85 86 87 dcl 1 apuhra (16) based (aphrp), 88 (2 esn bit (15), /* effective segment number for this cycle */ 89 2 bsy bit (2), /* source of ESN above */ 90 2 fdsptw bit (1), /* fetch of dseg PTW */ 91 2 mdsptw bit (1), /* mod of dseg PTW */ 92 2 dfsdw bit (1), /* xxxxxx */ 93 2 fptw bit (1), /* fetch PTW */ 94 2 fptw2 bit (1), /* fetch PTW + 1 */ 95 2 mptw bit (1), /* modify PTW */ 96 2 fanp bit (1), /* fetch final add from non-paged seg */ 97 2 fap bit (1), /* xxxxx */ 98 2 sdwmf bit (1), /* SDW match in AM */ 99 2 sdwamr bit (4), /* AM register that holds SDW */ 100 2 ptwmf bit (1), /* PTW match in AM */ 101 2 ptwamr bit (4), /* AM register that holds PTW */ 102 2 flt bit (1), /* ACV or DF flt caused by this cycle */ 103 2 finadd bit (24), /* absolute address of this cycle */ 104 2 trr bit (3), /* value of tpr.trr for this cycle */ 105 2 apu_pad1 bit (7), 106 2 flthld bit (1), /* an ACV or DF flt is waiting to be processed */ 107 2 apu_pad2 bit (1))unaligned; 108 109 110 dcl 1 duhra (16) based (duhrp) aligned, 111 (2 pol bit (1), /* preparing operand length */ 112 2 pop bit (1), /* preparing pointer */ 113 2 ndesc bit (1), /* need descriptor */ 114 2 seladr bit (1), /* select address register */ 115 2 dlendr bit (1), /* length = direct */ 116 2 dfrst bit (1), /* processing desc. for first time */ 117 2 exr bit (1), /* extended register modification */ 118 2 ldfrst bit (1), /* last cycle of dfrst above */ 119 2 dulea bit (1), /* DU load and effective add. */ 120 2 dusea bit (1), /* DU store and effective add. */ 121 2 redo bit (1), /* redo - no update of ptrs. and lngh. */ 122 2 wcws bit (1), /* load word count < word size */ 123 2 exh bit (1), /* exhaust */ 124 2 eseq bit (1), /* end of sequence */ 125 2 einst bit (1), /* end of instruction */ 126 2 durw bit (1), /* DU read or write */ 127 2 ptra bit (2), /* PR address bits 0 and 1 */ 128 2 fai1 bit (1), /* active/inactive desc. 1 */ 129 2 fai2 bit (1), /* active/inactive desc. 2 */ 130 2 fai3 bit (1), /* active/inactive desc. 3 */ 131 2 du_wrd bit (1), /* word type inst. */ 132 2 nine bit (1), /* nine bit type inst. */ 133 2 six bit (1), /* six bit type inst. */ 134 2 four bit (1), /* four bit type inst. */ 135 2 one bit (1), /* one bit type inst */ 136 2 du_pad1 bit (4), 137 2 samplint bit (1), /* sample for mid inst. intrp. */ 138 2 sfcsq bit (1), /* specific first count of sequence */ 139 2 adjlen bit (1), /* adjust length */ 140 2 mif bit (1), /* mid inst. intrp. indicator */ 141 2 inhibstc1 bit (1), /* inhibit sct1 inst. */ 142 2 du_pad2 bit (1), 143 2 duidl bit (1), /* DU idle */ 144 2 dcldgta bit (1), /* desc. load gates A */ 145 2 dcldgtb bit (1), /* desc. load gates B */ 146 2 dcldgtc bit (1), /* desc. load gates C */ 147 2 nopl1 bit (1), /* alignment cnt. for 1st numeric op. ld. */ 148 2 nopgl1 bit (1), /* numeric op. 1 gate load */ 149 2 nopl2 bit (1), /* alignment cnt. for 2nd numeric op. ld. */ 150 2 nopgl2 bit (1), /* numeric op. 2 gate load */ 151 2 aoplg1 bit (1), /* alphanum. op. 1 gate load */ 152 2 aoplg2 bit (1), /* alphanum. op. 2 gate load */ 153 2 lrwrg1 bit (1), /* load rewrite reg. gate 1 */ 154 2 lrwrg2 bit (1), /* load rewrite reg. gate 2 */ 155 2 dataav_du bit (1), /* data available */ 156 2 rw1rl bit (1), /* rewrite one reg. loaded */ 157 2 numstg bit (1), /* numeric store gate */ 158 2 anstg bit (1), /* alpha-numeric store gate */ 159 2 opav bit (1), /* operand available */ 160 2 endseq_du bit (1), /* end sequence */ 161 2 len128 bit (1), /* length < 128 */ 162 2 charop bit (1), /* character operation */ 163 2 anpk bit (1), /* alphanumeric packing cycle */ 164 2 exmop bit (1), /* execute MOP */ 165 2 blnk bit (1), /* blanking ind. */ 166 2 du_pad3 bit (1), 167 2 bde bit (1), /* binary to decimal ind. */ 168 2 dbe bit (1), /* decimal to binary ind. */ 169 2 shft bit (1), /* shift ind. */ 170 2 flt bit (1), /* floating ind. */ 171 2 rnd bit (1), /* round ind. */ 172 2 addsub bit (1), /* add-subtract ind. */ 173 2 multdiv bit (1), /* multiply-divide ind. */ 174 2 expon bit (1), /* exponent ind. */ 175 2 du_pad4 bit (4))unaligned; 176 177 178 /* END INCLUDE FILE ... history_regs.incl.pl1 */