1 2 /* BEGIN INCLUDE FILE ... history_regs_dps8.incl.pl1 3 * ... created by R. L. Coppola 8/80. */ 4 /* Modified Sept, 1981 by Rich Coppola to reflect changes made in the CPU */ 5 6 dcl (du_ouhrp, cuhrp, aphrp1, aphrp2, hr_data_ptr) ptr; 7 dcl nregs fixed bin; /* number of history registers saved (16/64) */ 8 9 10 dcl 1 ext_hr based (hr_data_ptr), /* History Register data */ 11 2 DU_OU (nregs), 12 3 even bit (36), 13 3 odd bit (36), 14 2 CU (nregs), 15 3 even bit (36), 16 3 odd bit (36), 17 2 AU2 (nregs), 18 3 even bit (36), 19 3 odd bit (36), 20 2 AU1 (nregs), 21 3 even bit (36), 22 3 odd bit (36); 23 24 25 26 dcl du_ou_offset fixed bin init (0), /* offsets to hr data within the hr data block */ 27 cu_offset fixed bin init (32), 28 au_offset2 fixed bin init (64), 29 au_offset1 fixed bin init (96); 30 31 32 dcl 1 cuhra (nregs) like cuhr; /* copy of HR data (corrected) */ 33 34 dcl 1 cuhr (nregs) based (cuhrp) aligned, 35 (2 pia bit (1), /* preparing instruction address */ 36 2 poa bit (1), /* preparing operand address */ 37 2 riw bit (1), /* requesting indirect word */ 38 2 siw bit (1), /* restoring indirect word */ 39 2 pot bit (1), /* preparing operand tally */ 40 2 pon bit (1), /* preparing operand address */ 41 2 raw bit (1), /* requesting alter-rewrite word (complemented) */ 42 2 saw bit (1), /* restoring alter-rewrite word */ 43 2 rtrgo bit (1), /* remember transfer go - condition met */ 44 2 xde bit (1), /* XED from even location */ 45 2 xdo bit (1), /* XED from odd location */ 46 2 ic bit (1), /* even/odd inst. pair */ 47 2 rpts bit (1), /* repeat operation */ 48 2 portf bit (1), /* memory cycle to port on previous cycle */ 49 2 internal bit (1), /* memory cycle to cache or direct on previous cycle */ 50 2 pai bit (1), /* prepare interrupt address */ 51 2 pfa bit (1), /* prepare FLT address */ 52 2 master_mode bit (1), /* in master mode */ 53 2 op_code bit (10), /* op code of inst */ 54 2 inhib bit (1), /* inhibit int bit */ 55 2 its_flag bit (1), /* ar reg mod flag */ 56 2 tag bit (6), /* tag field of instr */ 57 2 ca_value bit (24), /* 24 bit address field of inst */ 58 2 pcmd bit (5), /* processor command register */ 59 2 xint bit (1), /* execute interrupt */ 60 2 ins_fetch bit (1), /* inst fetch */ 61 2 cache_rd bit (1), /* cache read cycle this cycle */ 62 2 mem_rd bit (1), /* memory read this cycle */ 63 2 mem_sto bit (1), /* memory store this cycle */ 64 2 pib bit (1), /* port interface busy */ 65 2 cache_flush bit (1)) unaligned; 66 67 dcl 1 du_ouhr (nregs) based (du_ouhrp) aligned, 68 (2 fanld1 bit (1), /* alpha-num load desc 1 (complemented) */ 69 2 fanld2 bit (1), /* alpha-num load desc 2 (complemented) */ 70 2 fanstr bit (1), /* alpha-num store (complemented) */ 71 2 fldwrt1 bit (1), /* load re-write reg 1 (complemented) */ 72 2 fldwrt2 bit (1), /* load re-write reg 2 (complemented) */ 73 2 fnld1 bit (1), /* numeric load desc 1 (complemented) */ 74 2 fnld2 bit (1), /* numeric load desc 2 (complemented) */ 75 2 endseqf bit (1), /* end sequence flag */ 76 2 fdud bit (1), /* decimal unit idle (complemented) */ 77 2 fgstr bit (1), /* general store flag (complemented) */ 78 2 endseq bit (1), /* end of sequence (complemented) */ 79 2 nine bit (1), /* 9-bit char. operation */ 80 2 six bit (1), /* 6-bit char. operation */ 81 2 four bit (1), /* 4-bit char operation */ 82 2 du_bit bit (1), /* Bit operation */ 83 2 du_word bit (1), /* Word operation */ 84 2 ptr1 bit (1), /* select ptr 1 */ 85 2 ptr2 bit (1), /* select ptr 2 */ 86 2 ptr3 bit (1), /* select ptr 3 */ 87 2 fpop bit (1), /* prepare operand pointer */ 88 2 fgeac bit (1), /* add cycle gate C (complemented) */ 89 2 fgeae bit (1), /* add cycle gate E (complemented) */ 90 2 fgeaf bit (1), /* add cycle gate F(complemented) */ 91 2 fgeah bit (1), /* add cycle gate H (complemented) */ 92 2 fgldp1 bit (1), /* load PTR #1 (complemented) */ 93 2 fsweq bit (1), /* single word sequence flag (complemented) */ 94 2 fgch bit (1), /* character cycle (complemented) */ 95 2 dfrst bit (1), /* processing descriptor for first time */ 96 2 exh bit (1), /* exhaust */ 97 2 fgadd bit (1), /* add cycle (complemented) */ 98 2 intrptd bit (1), /* interrupted */ 99 2 dcode, 100 3 gldp2 bit (1), /* ldp2 (complemented) */ 101 3 gemc bit (1), /* exponent control */ 102 3 gbda bit (1), /* bin to dec gate A */ 103 3 gsp5 bit (1), /* shift timing gate */ 104 3 dcode_pad bit (1), 105 2 ict bit (18), /* Instruction counter */ 106 2 rs bit (9), /* OU op-code register (RS0-8) */ 107 2 ir_reg, /* the indicator reg */ 108 3 zero_ bit (1), 109 3 sign_ bit (1), 110 3 carry_ bit (1), 111 3 ovfl_ bit (1), 112 3 eovfl_ bit (1), 113 3 eufl_ bit (1), 114 3 oflm_ bit (1), 115 3 hex_ bit (1), 116 2 dtrgo bit (1)) unaligned; /* transfer go */ 117 118 119 dcl 1 apuhr1 (nregs) based (aphrp1) aligned, 120 (2 esn bit (15), /* effective segment number for this cycle */ 121 /* bits 11-14 contain the */ 122 /* SDWAM addr selected */ 123 2 piapgbsy bit (1), /* ins fetch across a page bndry */ 124 2 piaoosb bit (1), /* ins fetch OOSB */ 125 2 fdsptw bit (1), /* fetch of dseg PTW */ 126 2 mdsptw bit (1), /* mod of dseg PTW */ 127 2 fsdwp bit (1), /* fetch paged SDW */ 128 2 fptw bit (1), /* fetch PTW */ 129 2 fptw2 bit (1), /* fetch PTW + 1 */ 130 2 mptw bit (1), /* modify PTW */ 131 2 fanp bit (1), /* fetch final add from non-paged seg */ 132 2 fap bit (1), /* fetch final addr paged */ 133 2 mtchsdw bit (1), /* SDW match in AM */ 134 2 sdwmf bit (1), /* SDWAM match occurred and used */ 135 2 bsy bit (2), /* data source for ESN */ 136 /* 00 = from ppr.psr */ 137 /* 01 = from prn.tsr */ 138 /* 10 = from tpr.snr */ 139 /* 11 = from tpr.ca */ 140 2 ptwmf bit (1), /* PTW match in AM */ 141 2 mtchptw bit (1), /* PTWAM match occurred */ 142 2 ptwaddr bit (4), /* addr sel for PTWAM (tpr.ca)4,7 */ 143 2 flt bit (1), /* ACV or DF flt caused by this cycle */ 144 2 finadd bit (24), /* absolute address of this cycle */ 145 2 trr bit (3), /* value of tpr.trr for this cycle */ 146 2 sdwerr bit (1), /* multi-mtch or parity err in SDWAM */ 147 2 sdwlvl bit (2), /* SDWAM level selected */ 148 2 cache_used bit (1), /* CPU used cache for this cycle */ 149 2 ptwerr bit (1), /* multi-match or parity err in PTWAM */ 150 2 ptwlvl bit (2), /* PTWAM level selected */ 151 2 flthld bit (1), /* an ACV or DF flt is waiting to be processed */ 152 2 apu_pad2 bit (1))unaligned; 153 154 dcl 1 apuhr2 (nregs) based (aphrp2) aligned, 155 (2 CA bit (18), /* tpr.ca */ 156 2 opcode bit (10), /* opcode from cur instr */ 157 2 inhibit_bit bit (1), /* interrupt inhib bit */ 158 2 pr_flag bit (1), /* PR mod flag */ 159 2 TAG bit (6), /* mod. tag field */ 160 2 pad1 bit (36))unaligned; 161 162 163 /* END INCLUDE FILE ... history_regs_dpse.incl.pl1 */