1 /* BEGIN INCLUDE FILE ... history_regs.incl.pl1 ... last modified 6/72 */ 2 3 4 dcl (ouhrp, cuhrp, aphrp, duhrp) ptr; 5 6 dcl 1 cuhr based(cuhrp) aligned, 7 (2 pia bit(1), /* preparing instruction address */ 8 2 poa bit(1), /* preparing operand address */ 9 2 riw bit(1), /* requesting indirect word */ 10 2 siw bit(1), /* restoring indirect word */ 11 2 pot bit(1), /* preparing operand tally */ 12 2 pon bit(1), /* preparing operand address */ 13 2 raw bit(1), /* requesting alter-rewrite word */ 14 2 saw bit(1), /* restoring alter-rewrite word */ 15 2 trgo bit(1), /* transfer go - condition met */ 16 2 xde bit(1), /* XED from even location */ 17 2 xdo bit(1), /* XED from odd location */ 18 2 ic bit(1), /* even/odd inst. pair */ 19 2 rpts bit(1), /* repeat operation */ 20 2 wi bit(1), /* wait for instruction fetch */ 21 2 ar bit(1), /* address reg valid */ 22 2 nxip bit(1), /* not an xip address */ 23 2 nflt bit(1), /* not an FLT address */ 24 2 np bit(1), /* not in privilaged mode */ 25 2 inst bit(18), /* op code and tag of inst */ 26 2 addr bit(18), /* address field of inst */ 27 2 pcmd bit(5), /* processor command register */ 28 2 psl bit(4), /* port select lines */ 29 2 xec_int bit(1), /* execute interrupt */ 30 2 ins_fetch bit(1), /* inst fetch */ 31 2 cus bit(1), /* control unit store */ 32 2 ous bit(1), /* operations unit store */ 33 2 cul bit(1), /* control unit load */ 34 2 oul bit(1), /* operations unit load */ 35 2 dir bit(1), /* direct cycle */ 36 2 npcb bit(1), /* port logic not busy */ 37 2 pib bit(1)) unaligned; /* port interface busy */ 38 39 dcl 1 cuhra(0 : 15) based(cuhrp) aligned, 40 (2 pia bit(1), /* preparing instruction address */ 41 2 poa bit(1), /* preparing operand address */ 42 2 riw bit(1), /* requesting indirect word */ 43 2 siw bit(1), /* restoring indirect word */ 44 2 pot bit(1), /* preparing operand tally */ 45 2 pon bit(1), /* preparing operand address */ 46 2 raw bit(1), /* requesting alter-rewrite word */ 47 2 saw bit(1), /* restoring alter-rewrite word */ 48 2 trgo bit(1), /* transfer go - condition met */ 49 2 xde bit(1), /* XED from even location */ 50 2 xdo bit(1), /* XED from odd location */ 51 2 ic bit(1), /* even/odd inst. pair */ 52 2 rpts bit(1), /* repeat operation */ 53 2 wi bit(1), /* wait for instruction fetch */ 54 2 ar bit(1), /* address reg valid */ 55 2 nxip bit(1), /* not an xip address */ 56 2 nflt bit(1), /* not an FLT address */ 57 2 np bit(1), /* not in privilaged mode */ 58 2 inst bit(18), /* op code and tag of inst */ 59 2 addr bit(18), /* address field of inst */ 60 2 pcmd bit(5), /* processor command register */ 61 2 psl bit(4), /* port select lines */ 62 2 xec_int bit(1), /* execute interrupt */ 63 2 ins_fetch bit(1), /* inst fetch */ 64 2 cus bit(1), /* control unit store */ 65 2 ous bit(1), /* operations unit store */ 66 2 cul bit(1), /* control unit load */ 67 2 oul bit(1), /* operations unit load */ 68 2 dir bit(1), /* direct cycle */ 69 2 npcb bit(1), /* port logic not busy */ 70 2 pib bit(1)) unaligned; /* port interface busy */ 71 72 dcl 1 ouhr based(ouhrp) aligned, 73 (2 nopc bit(9), /* next inst. op code */ 74 2 itw bit(1), /* IT tally word 6/9 bit data */ 75 2 ntg bit(3), /* next inst tag field */ 76 2 cmod bit(1), /* character modification */ 77 2 dir bit(1), /* direct modification */ 78 2 efad bit(2), /* LREG/SREG effective addr */ 79 2 pad0 bit(1), 80 2 rp bit(9), /* copy of RP reg */ 81 2 opbf bit(1), /* OU op code buffer full */ 82 2 frpf bit(1), /* primary register full */ 83 2 srf bit(1), /* secondary register full */ 84 2 fgin bit(1), /* first cycle for all OU */ 85 2 fgos bit(1), /* second cycle for OU - multiple OP */ 86 2 fgd1 bit(1), /* first divide cycle */ 87 2 fgd2 bit(1), /* second divide cycle */ 88 2 fgoe bit(1), /* exponent compare cycle */ 89 2 fgoa bit(1), /* mamtissa alignment cycle */ 90 2 fgom bit(1), /* general OU cycle */ 91 2 fgon bit(1), /* normalize cycle */ 92 2 fgof bit(1), /* final cycle */ 93 2 fstr bit(1), /* OU store data available */ 94 2 dn bit(1), /* data not available */ 95 2 an bit(1), /* A reg not in use */ 96 2 qn bit(1), /* Q reg not used */ 97 2 x0n bit(1), /* X0 not in use */ 98 2 x1n bit(1), /* X1 not in use */ 99 2 x2n bit(1), /* X2 not in use */ 100 2 x3n bit(1), /* X3 not in use */ 101 2 x4n bit(1), /* X4 not in use */ 102 2 x5n bit(1), /* X5 not in use */ 103 2 x6n bit(1), /* X6 not in use */ 104 2 x7n bit(1), /* X7 not in use */ 105 2 pad1 bit(3), 106 2 ict bit(18)) unaligned; /* address of OU inst */ 107 108 dcl 1 ouhra(0 : 15) based(ouhrp) aligned, 109 (2 nopc bit(9), /* next inst. op code */ 110 2 itw bit(1), /* IT tally word 6/9 bit data */ 111 2 ntg bit(3), /* next inst tag field */ 112 2 cmod bit(1), /* character modification */ 113 2 dir bit(1), /* direct modification */ 114 2 efad bit(2), /* LREG/SREG effective addr */ 115 2 pad0 bit(1), 116 2 rp bit(9), /* copy of RP reg */ 117 2 opbf bit(1), /* OU op code buffer full */ 118 2 frpf bit(1), /* primary register full */ 119 2 srf bit(1), /* secondary register full */ 120 2 fgin bit(1), /* first cycle for all OU */ 121 2 fgos bit(1), /* second cycle for OU - multiple OP */ 122 2 fgd1 bit(1), /* first divide cycle */ 123 2 fgd2 bit(1), /* second divide cycle */ 124 2 fgoe bit(1), /* exponent compare cycle */ 125 2 fgoa bit(1), /* mamtissa alignment cycle */ 126 2 fgom bit(1), /* general OU cycle */ 127 2 fgon bit(1), /* normalize cycle */ 128 2 fgof bit(1), /* final cycle */ 129 2 fstr bit(1), /* OU store data available */ 130 2 dn bit(1), /* data not available */ 131 2 an bit(1), /* A reg not in use */ 132 2 qn bit(1), /* Q reg not used */ 133 2 x0n bit(1), /* X0 not in use */ 134 2 x1n bit(1), /* X1 not in use */ 135 2 x2n bit(1), /* X2 not in use */ 136 2 x3n bit(1), /* X3 not in use */ 137 2 x4n bit(1), /* X4 not in use */ 138 2 x5n bit(1), /* X5 not in use */ 139 2 x6n bit(1), /* X6 not in use */ 140 2 x7n bit(1), /* X7 not in use */ 141 2 pad1 bit(3), 142 2 ict bit(18)) unaligned; /* address of OU inst */ 143 144 dcl 1 apuhr based(aphrp) aligned, 145 (2 esn bit(15), /* effective segment number for this cycle */ 146 2 bsy bit(2), /* source of ESN above */ 147 2 fdsptw bit(1), /* fetch of dseg PTW */ 148 2 mdsptw bit(1), /* mod of dseg PTW */ 149 2 dfsdw bit(1), /* xxxxxx */ 150 2 fptw bit(1), /* fetch PTW */ 151 2 fptw2 bit(1), /* fetch PTW + 1 */ 152 2 mptw bit(1), /* modify PTW */ 153 2 fanp bit(1), /* fetch final add from non-paged seg */ 154 2 fap bit(1), /* xxxxx */ 155 2 sdwmf bit(1), /* SDW match in AM */ 156 2 sdwamr bit(4), /* AM register that holds SDW */ 157 2 ptwmf bit(1), /* PTW match in AM */ 158 2 ptwamr bit(4), /* AM register that holds PTW */ 159 2 flt bit(1), /* ACV or DF flt caused by this cycle */ 160 2 add bit(24), /* absolute address of this cycle */ 161 2 trr bit(3), /* value of tpr.trr for this cycle */ 162 2 apu_pad1 bit(7), 163 2 flthld bit(1), /* an ACV or DF flt is waiting to be processed */ 164 2 apu_pad2 bit(1) )unaligned; 165 166 167 dcl 1 apuhra(0 : 15) based(aphrp), 168 (2 esn bit(15), /* effective segment number for this cycle */ 169 2 bsy bit(2), /* source of ESN above */ 170 2 fdsptw bit(1), /* fetch of dseg PTW */ 171 2 mdsptw bit(1), /* mod of dseg PTW */ 172 2 dfsdw bit(1), /* xxxxxx */ 173 2 fptw bit(1), /* fetch PTW */ 174 2 fptw2 bit(1), /* fetch PTW + 1 */ 175 2 mptw bit(1), /* modify PTW */ 176 2 fanp bit(1), /* fetch final add from non-paged seg */ 177 2 fap bit(1), /* xxxxx */ 178 2 sdwmf bit(1), /* SDW match in AM */ 179 2 sdwamr bit(4), /* AM register that holds SDW */ 180 2 ptwmf bit(1), /* PTW match in AM */ 181 2 ptwamr bit(4), /* AM register that holds PTW */ 182 2 flt bit(1), /* ACV or DF flt caused by this cycle */ 183 2 add bit(24), /* absolute address of this cycle */ 184 2 trr bit(3), /* value of tpr.trr for this cycle */ 185 2 apu_pad1 bit(7), 186 2 flthld bit(1), /* an ACV or DF flt is waiting to be processed */ 187 2 apu_pad2 bit(1) )unaligned; 188 189 190 dcl 1 duhr based(duhrp) aligned, 191 (2 pol bit(1), /* preparing operand length */ 192 2 pop bit(1), /* preparing pointer */ 193 2 ndesc bit(1), /* need descriptor */ 194 2 seladr bit(1), /* select address register */ 195 2 dlendr bit(1), /* length = direct */ 196 2 dfrst bit(1), /* processing desc. for first time */ 197 2 exr bit(1), /* extended register modification */ 198 2 ldfrst bit(1), /* last cycle of dfrst above */ 199 2 dulea bit(1), /* DU load and effective add. */ 200 2 dusea bit(1), /* DU store and effective add. */ 201 2 redo bit(1), /* redo - no update of ptrs. and lngh. */ 202 2 wcws bit(1), /* load word count < word size */ 203 2 exh bit(1), /* exhaust */ 204 2 eseq bit(1), /* end of sequence */ 205 2 einst bit(1), /* end of instruction */ 206 2 durw bit(1), /* DU read or write */ 207 2 pradb0 bit(1), /* PR address bit 0 */ 208 2 pradb1 bit(1), /* PR address bit 1 */ 209 2 aidesc bit(3), /* active/inactive desc. 1 2 and 3 */ 210 2 wrd bit(1), /* word type inst. */ 211 2 nine bit(1), /* nine bit type inst. */ 212 2 six bit(1), /* six bit type inst. */ 213 2 four bit(1), /* four bit type inst. */ 214 2 du_pad1 bit(4), 215 2 samplint bit(1), /* sample for mid inst. intrp. */ 216 2 sfcsq bit(1), /* specific first count of sequence */ 217 2 adjlen bit(1), /* adjust length */ 218 2 intind bit(1), /* mid inst. intrp. indicator */ 219 2 inhibstc1 bit(1), /* inhibit sct1 inst. */ 220 2 du_pad2 bit(1), 221 2 duidl bit(1), /* DU idle */ 222 2 dcldgt bit(3), /* desc. load gates A B and C */ 223 2 nopl1 bit(1), /* alignment cnt. for 1st numeric op. ld. */ 224 2 nopgl1 bit(1), /* numeric op. 1 gate load */ 225 2 nopl2 bit(1), /* alignment cnt. for 2nd numeric op. ld. */ 226 2 nopgl2 bit(1), /* numeric op. 2 gate load */ 227 2 aoplg1 bit(1), /* alphanum. op. 1 gate load */ 228 2 aoplg2 bit(1), /* alphanum. op. 2 gate load */ 229 2 lrwrg1 bit(1), /* load rewrite reg. gate 1 */ 230 2 lrwrg2 bit(1), /* load rewrite reg. gate 2 */ 231 2 dataav bit(1), /* data available */ 232 2 rw1rl bit(1), /* rewrite one reg. loaded */ 233 2 numstg bit(1), /* numeric store gate */ 234 2 anstg bit(1), /* alpha-numeric store gate */ 235 2 opav bit(1), /* operand available */ 236 2 endseq bit(1), /* end sequence */ 237 2 len128 bit(1), /* length < 128 */ 238 2 charop bit(1), /* character operation */ 239 2 anpk bit(1), /* alphanumeric packing cycle */ 240 2 exmop bit(1), /* execute MOP */ 241 2 blnk bit(1), /* blanking ind. */ 242 2 du_pad3 bit(1), 243 2 bde bit(1), /* binary to decimal ind. */ 244 2 dbe bit(1), /* decimal to binary ind. */ 245 2 shft bit(1), /* shift ind. */ 246 2 flt bit(1), /* floating ind. */ 247 2 rnd bit(1), /* round ind. */ 248 2 addsub bit(1), /* add-subtract ind. */ 249 2 multdiv bit(1), /* multiply-divide ind. */ 250 2 expon bit(1), /* exponent ind. */ 251 2 du_pad4 bit(4))unaligned; 252 253 dcl 1 duhra(0 : 15) based(duhrp) aligned, 254 (2 pol bit(1), /* preparing operand length */ 255 2 pop bit(1), /* preparing pointer */ 256 2 ndesc bit(1), /* need descriptor */ 257 2 seladr bit(1), /* select address register */ 258 2 dlendr bit(1), /* length = direct */ 259 2 dfrst bit(1), /* processing desc. for first time */ 260 2 exr bit(1), /* extended register modification */ 261 2 ldfrst bit(1), /* last cycle of dfrst above */ 262 2 dulea bit(1), /* DU load and effective add. */ 263 2 dusea bit(1), /* DU store and effective add. */ 264 2 redo bit(1), /* redo - no update of ptrs. and lngh. */ 265 2 wcws bit(1), /* load word count < word size */ 266 2 exh bit(1), /* exhaust */ 267 2 eseq bit(1), /* end of sequence */ 268 2 einst bit(1), /* end of instruction */ 269 2 durw bit(1), /* DU read or write */ 270 2 pradb0 bit(1), /* PR address bit 0 */ 271 2 pradb1 bit(1), /* PR address bit 1 */ 272 2 aidesc bit(3), /* active/inactive desc. 1 2 and 3 */ 273 2 wrd bit(1), /* word type inst. */ 274 2 nine bit(1), /* nine bit type inst. */ 275 2 six bit(1), /* six bit type inst. */ 276 2 four bit(1), /* four bit type inst. */ 277 2 du_pad1 bit(4), 278 2 samplint bit(1), /* sample for mid inst. intrp. */ 279 2 sfcsq bit(1), /* specific first count of sequence */ 280 2 adjlen bit(1), /* adjust length */ 281 2 intind bit(1), /* mid inst. intrp. indicator */ 282 2 inhibstc1 bit(1), /* inhibit sct1 inst. */ 283 2 du_pad2 bit(1), 284 2 duidl bit(1), /* DU idle */ 285 2 dcldgt bit(3), /* desc. load gates A B and C */ 286 2 nopl1 bit(1), /* alignment cnt. for 1st numeric op. ld. */ 287 2 nopgl1 bit(1), /* numeric op. 1 gate load */ 288 2 nopl2 bit(1), /* alignment cnt. for 2nd numeric op. ld. */ 289 2 nopgl2 bit(1), /* numeric op. 2 gate load */ 290 2 aoplg1 bit(1), /* alphanum. op. 1 gate load */ 291 2 aoplg2 bit(1), /* alphanum. op. 2 gate load */ 292 2 lrwrg1 bit(1), /* load rewrite reg. gate 1 */ 293 2 lrwrg2 bit(1), /* load rewrite reg. gate 2 */ 294 2 dataav bit(1), /* data available */ 295 2 rw1rl bit(1), /* rewrite one reg. loaded */ 296 2 numstg bit(1), /* numeric store gate */ 297 2 anstg bit(1), /* alpha-numeric store gate */ 298 2 opav bit(1), /* operand available */ 299 2 endseq bit(1), /* end sequence */ 300 2 len128 bit(1), /* length < 128 */ 301 2 charop bit(1), /* character operation */ 302 2 anpk bit(1), /* alphanumeric packing cycle */ 303 2 exmop bit(1), /* execute MOP */ 304 2 blnk bit(1), /* blanking ind. */ 305 2 du_pad3 bit(1), 306 2 bde bit(1), /* binary to decimal ind. */ 307 2 dbe bit(1), /* decimal to binary ind. */ 308 2 shft bit(1), /* shift ind. */ 309 2 flt bit(1), /* floating ind. */ 310 2 rnd bit(1), /* round ind. */ 311 2 addsub bit(1), /* add-subtract ind. */ 312 2 multdiv bit(1), /* multiply-divide ind. */ 313 2 expon bit(1), /* exponent ind. */ 314 2 du_pad4 bit(4))unaligned; 315 316 /* END INCLUDE FILE ... history_regs.incl.pl1 */