1 /* BEGIN include file adp_scu.incl.pl1 */
 2 
 3 /* This include file describes the data stored by the scu instruction on
 4 the adp processor.
 5 
 6 Written 9/83 by Keith Loepere. */
 7 
 8 /* format: style4,indattr,ifthenstmt,ifthen,idind33,^indcomtxt */
 9 
10 dcl  adp_scup                         ptr;
11 
12 dcl  1 adp_scu                        based (adp_scup) aligned,
13 
14 /* Word 0 */
15 
16        2 unknown1                     bit (14) unal,
17        2 itc                          bit (4) unal,         /* count of indirect tally words in chain */
18        2 op_code                      bit (10) unal,        /* normally of faulting instruction */
19        2 i                            bit (1) unal,         /* interrupt inhibit bit of faulting instr */
20        2 a                            bit (1) unal,         /* indirect via pointer register */
21        2 tag                          bit (6) unal,         /* tag field */
22 
23 /* Word 1 */
24 
25        2 (
26        iro,                                                 /* illegal ring order */
27        oeb,                                                 /* out of execute bracket */
28        e_off,                                               /* no execute permission */
29        orb,                                                 /* out of read bracket */
30        r_off,                                               /* no read permission */
31        owb,                                                 /* out of write bracket */
32        w_off,                                               /* no write permission */
33        no_ga,                                               /* not a gate */
34        ocb,                                                 /* out of call bracket */
35        ocall,                                               /* outward call */
36        boc,                                                 /* bad outward call */
37        zero1,
38        crt,                                                 /* cross ring transfer */
39        ralr,                                                /* ring alarm */
40        zero2,
41        oosb,                                                /* out of segment bounds */
42        zero3,
43        zero4,
44        ioc,                                                 /* illegal op code */
45        it,                                                  /* illegal tag */
46        im,                                                  /* illegal mode */
47        if,                                                  /* fault occured during instrcution fetch */
48        zero5,
49        fsdw,                                                /* fault during sdw fetch */
50        zero6,
51        ied                                                  /* illegal eis digit */
52        )                              bit (1) unal,
53        2 unknown2                     bit (4) unal,
54        2 hw_ind                       bit (6) unal,         /* hw restart indicators */
55 
56 /* Word 2 */
57 
58        2 hw_info2                     bit (36),             /* restart info */
59 
60 /* Word 3 */
61 
62        2 hw_info3                     bit (36),             /* restart info */
63 
64 /* Word 4 */
65 
66        2 ilc                          bit (18) unal,        /* instruction counter */
67        2 ir                           bit (18) unal,        /* indicator registor */
68 
69 /* Word 5 */
70 
71        2 unknown3                     bit (9) unal,
72        2 tprv                         bit (1) unal,         /* tpr valid */
73        2 zero7                        bit (1) unal,
74        2 fi_flag                      bit (1) unal,         /* 1 => interrupt, 0 => fault */
75        2 fi_num                       bit (5) unal,         /* (fault/interrupt) number */
76        2 zero8                        bit (1) unal,
77        2 unknown4                     bit (2) unal,
78        2 cpu_no                       bit (2) unal,         /* CPU number */
79        2 unknown5                     bit (14) unal,
80 
81 /* Word 6 */
82 
83        2 zero9                        bit (3) unal,
84        2 psr                          bit (15) unal,        /* procedure segment register */
85        2 prr                          bit (3) unal,         /* procedure ring register */
86        2 zero10                       bit (4) unal,
87        2 p                            bit (1) unal,         /* procedure privileged bit */
88        2 zero11                       bit (4) unal,
89        2 tag43                        bit (6) unal,         /* has its 43 tag */
90 
91 /* Word 7 */
92 
93        2 trr                          bit (3) unal,         /* temporary ring register */
94        2 tsr                          bit (15) unal,        /* temporary segment register */
95        2 ca                           bit (18) unal;        /* computed address */
96 
97 /* END include file adp_scu.incl.pl1 */