TRR                27 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               140 src/dps8/doAppendCycleABSA.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               151 src/dps8/doAppendCycleABSA.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               281 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                25 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               154 src/dps8/doAppendCycleAPUDataRMW.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               165 src/dps8/doAppendCycleAPUDataRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               187 src/dps8/doAppendCycleAPUDataRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               190 src/dps8/doAppendCycleAPUDataRMW.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TRR               191 src/dps8/doAppendCycleAPUDataRMW.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TRR               200 src/dps8/doAppendCycleAPUDataRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               348 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                25 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               149 src/dps8/doAppendCycleAPUDataRead.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               160 src/dps8/doAppendCycleAPUDataRead.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               299 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                25 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               152 src/dps8/doAppendCycleAPUDataStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               155 src/dps8/doAppendCycleAPUDataStore.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TRR               156 src/dps8/doAppendCycleAPUDataStore.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TRR               165 src/dps8/doAppendCycleAPUDataStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               301 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                61 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               245 src/dps8/doAppendCycleIndirectWordFetch.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               256 src/dps8/doAppendCycleIndirectWordFetch.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               437 src/dps8/doAppendCycleIndirectWordFetch.h           cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR);
TRR               441 src/dps8/doAppendCycleIndirectWordFetch.h   cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TRR               442 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(O) Set TRR to %o\n", cpu.TPR.TRR);
TRR               452 src/dps8/doAppendCycleIndirectWordFetch.h           cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR);
TRR               456 src/dps8/doAppendCycleIndirectWordFetch.h   cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TRR               457 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(P) Set TRR to %o\n", cpu.TPR.TRR);
TRR               471 src/dps8/doAppendCycleIndirectWordFetch.h           cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                72 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               312 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
TRR               314 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("acvFaults(C) ACV1 ! ( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TRR               329 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR > cpu.PPR.PRR)
TRR               330 src/dps8/doAppendCycleInstructionFetch.h     sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", cpu.TPR.TRR, cpu.PPR.PRR);
TRR               332 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR < cpu.PPR.PRR) {
TRR               377 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
TRR               379 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TRR               394 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.PPR.PRR != cpu.TPR.TRR) {
TRR               615 src/dps8/doAppendCycleInstructionFetch.h     cpu.PR[7].RNR = cpu.TPR.TRR;
TRR               643 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR == 0) {
TRR               660 src/dps8/doAppendCycleInstructionFetch.h           cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                25 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               154 src/dps8/doAppendCycleOperandRMW.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               165 src/dps8/doAppendCycleOperandRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               187 src/dps8/doAppendCycleOperandRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               190 src/dps8/doAppendCycleOperandRMW.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TRR               191 src/dps8/doAppendCycleOperandRMW.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TRR               200 src/dps8/doAppendCycleOperandRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               352 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                67 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               317 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               328 src/dps8/doAppendCycleOperandRead.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               388 src/dps8/doAppendCycleOperandRead.h           cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR);
TRR               424 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.SDW->R3) {
TRR               434 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR < cpu.SDW->R1) {
TRR               444 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.PPR.PRR) {
TRR               456 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o SDW->R2 %o\n", cpu.TPR.TRR, cpu.SDW->R2);
TRR               459 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               461 src/dps8/doAppendCycleOperandRead.h     cpu.TPR.TRR = cpu.SDW->R2;
TRR               464 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR);
TRR               484 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
TRR               486 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TRR               501 src/dps8/doAppendCycleOperandRead.h   if (cpu.PPR.PRR != cpu.TPR.TRR) {
TRR               763 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR == 0) {
TRR               777 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR == cpu.PPR.PRR) {
TRR               783 src/dps8/doAppendCycleOperandRead.h     cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR;
TRR               784 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("doAppendCycleOperandRead(N) STACK %05o TRR %o\n", cpu.DSBR.STACK, cpu.TPR.TRR);
TRR               789 src/dps8/doAppendCycleOperandRead.h   cpu.PR[7].RNR = cpu.TPR.TRR;
TRR               798 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.PRR = cpu.TPR.TRR;
TRR               814 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                25 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR               147 src/dps8/doAppendCycleOperandStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               150 src/dps8/doAppendCycleOperandStore.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TRR               151 src/dps8/doAppendCycleOperandStore.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TRR               160 src/dps8/doAppendCycleOperandStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               304 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR                25 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TRR                86 src/dps8/doAppendCycleRTCDOperandFetch.h     DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR);
TRR               178 src/dps8/doAppendCycleRTCDOperandFetch.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TRR               189 src/dps8/doAppendCycleRTCDOperandFetch.h     cpu.TPR.TRR = cpu.PPR.PRR;
TRR               350 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1);
TRR               374 src/dps8/doAppendCycleRTCDOperandFetch.h   if (cpu.TPR.TRR == 0) {
TRR               392 src/dps8/doAppendCycleRTCDOperandFetch.h           cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR               222 src/dps8/dps8_addrmods.c     cpu.TPR.TRR  = max3 (cpu.PR[n].RNR, cpu.RSDWH_R1, cpu.TPR.TRR);
TRR               261 src/dps8/dps8_addrmods.c                GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR,
TRR               262 src/dps8/dps8_addrmods.c                max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR));
TRR               264 src/dps8/dps8_addrmods.c     cpu.TPR.TRR  = max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR);
TRR              1206 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.TPR.TSR);
TRR              1276 src/dps8/dps8_append.c                 cpu.TPR.TSR, cpu.TPR.TRR);
TRR              1428 src/dps8/dps8_append.c         if (cpu.TPR.TRR > cpu.SDW->R2)
TRR              1441 src/dps8/dps8_append.c             cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1475 src/dps8/dps8_append.c             cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1478 src/dps8/dps8_append.c         if (cpu.TPR.TRR > cpu.SDW->R1)
TRR              1481 src/dps8/dps8_append.c                     cpu.TPR.TRR, cpu.SDW->R1);
TRR              1491 src/dps8/dps8_append.c             cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1520 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.SDW->R1 ||
TRR              1521 src/dps8/dps8_append.c         cpu.TPR.TRR > cpu.SDW->R2)
TRR              1525 src/dps8/dps8_append.c                 cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TRR              1541 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.PPR.PRR)
TRR              1543 src/dps8/dps8_append.c                 cpu.TPR.TRR, cpu.PPR.PRR);
TRR              1545 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.PPR.PRR)
TRR              1596 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.PPR.PRR);
TRR              1634 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.SDW->R3)
TRR              1645 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.SDW->R1)
TRR              1656 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.PPR.PRR)
TRR              1672 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.SDW->R2);
TRR              1675 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.SDW->R2)
TRR              1678 src/dps8/dps8_append.c         cpu.TPR.TRR = cpu.SDW->R2;
TRR              1681 src/dps8/dps8_append.c     DBGAPP ("do_append_cycle(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR);
TRR              1701 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.SDW->R1 ||
TRR              1702 src/dps8/dps8_append.c         cpu.TPR.TRR > cpu.SDW->R2)
TRR              1706 src/dps8/dps8_append.c                 cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TRR              1722 src/dps8/dps8_append.c     if (cpu.PPR.PRR != cpu.TPR.TRR)
TRR              2029 src/dps8/dps8_append.c     cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1);
TRR              2092 src/dps8/dps8_append.c         cpu.PR[7].RNR = cpu.TPR.TRR;
TRR              2120 src/dps8/dps8_append.c     if (cpu.TPR.TRR == 0)
TRR              2137 src/dps8/dps8_append.c     if (cpu.TPR.TRR == cpu.PPR.PRR)
TRR              2146 src/dps8/dps8_append.c         cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR;
TRR              2148 src/dps8/dps8_append.c                 cpu.DSBR.STACK, cpu.TPR.TRR);
TRR              2153 src/dps8/dps8_append.c     cpu.PR[7].RNR = cpu.TPR.TRR;
TRR              2162 src/dps8/dps8_append.c     cpu.PPR.PRR   = cpu.TPR.TRR;
TRR              2180 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR);
TRR              2184 src/dps8/dps8_append.c     cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TRR              2185 src/dps8/dps8_append.c     DBGAPP ("do_append_cycle(O) Set TRR to %o\n", cpu.TPR.TRR);
TRR              2195 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR);
TRR              2199 src/dps8/dps8_append.c     cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TRR              2200 src/dps8/dps8_append.c     DBGAPP ("do_append_cycle(P) Set TRR to %o\n", cpu.TPR.TRR);
TRR              2214 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TRR              2367 src/dps8/dps8_cpu.c                 cpu.TPR.TRR = 0;
TRR              2643 src/dps8/dps8_cpu.c                 cpu.TPR.TRR          = cpu.PPR.PRR;
TRR              2658 src/dps8/dps8_cpu.c                 cpu.TPR.TRR              = cpu.PPR.PRR;
TRR              2726 src/dps8/dps8_cpu.c                   cpu.TPR.TRR          = cpu.PPR.PRR;
TRR              3018 src/dps8/dps8_cpu.c                   cpu.TPR.TRR          = cpu.PPR.PRR;
TRR              3145 src/dps8/dps8_cpu.c               cpu.TPR.TRR = 0;
TRR              4431 src/dps8/dps8_cpu.c     putbits36_3 (& w1,       24, cpu.TPR.TRR);
TRR                78 src/dps8/dps8_cpu.h     word3   TRR; // The current effective ring number
TRR               557 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TRR               563 src/dps8/dps8_eis.c             cpu.TPR.TRR = p -> RNR;
TRR               577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TRR               589 src/dps8/dps8_eis.c             cpu.TPR.TRR = cpu.PPR.PRR;
TRR               605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TRR               615 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TRR               621 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TRR               640 src/dps8/dps8_eis.c         cpu.TPR.TRR = p -> RNR;
TRR               644 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TRR               659 src/dps8/dps8_eis.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               665 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TRR               680 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TRR               799 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TRR               803 src/dps8/dps8_eis.c         cpu.TPR.TRR = p -> RNR;
TRR               826 src/dps8/dps8_eis.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               840 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TRR               861 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TRR               865 src/dps8/dps8_eis.c         cpu.TPR.TRR = p -> RNR;
TRR               888 src/dps8/dps8_eis.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               902 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TRR              1270 src/dps8/dps8_eis.c                                             cpu.TPR.TRR,
TRR              1419 src/dps8/dps8_eis.c         e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TRR              1624 src/dps8/dps8_eis.c         e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TRR              1676 src/dps8/dps8_eis.c         e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TRR              1863 src/dps8/dps8_eis.c         e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TRR               118 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TRR               197 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               267 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               339 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               409 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               481 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               551 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               634 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               729 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               821 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               907 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR               948 src/dps8/dps8_iefp.c     cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1031 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1131 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1255 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1349 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1419 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1493 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1575 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1652 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1730 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1825 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1954 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TRR               417 src/dps8/dps8_ins.c     putbits36_3 (& words[2],  0, cpu.TPR.TRR);
TRR               693 src/dps8/dps8_ins.c     cpu.TPR.TRR         = getbits36_3  (words[2], 0);
TRR              1153 src/dps8/dps8_ins.c         cpu.TPR.TRR  = 0;
TRR              1905 src/dps8/dps8_ins.c             cpu.TPR.TRR = cpu.PPR.PRR;
TRR              1959 src/dps8/dps8_ins.c         cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR);
TRR              1961 src/dps8/dps8_ins.c         cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TRR              1965 src/dps8/dps8_ins.c                  n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR);
TRR              1983 src/dps8/dps8_ins.c           cpu.TPR.TRR  = 0;
TRR              2073 src/dps8/dps8_ins.c     cpu.TPR.TRR = cpu.PPR.PRR;
TRR              2715 src/dps8/dps8_ins.c             cpu.PR[n].RNR    = cpu.TPR.TRR;
TRR              2893 src/dps8/dps8_ins.c               cpu.PR[n].RNR = cpu.TPR.TRR;
TRR              3027 src/dps8/dps8_ins.c             cpu.PR[n].RNR    = cpu.TPR.TRR;
TRR              3464 src/dps8/dps8_ins.c           cpu.rA  = cpu.TPR.TRR & MASK3;
TRR              6916 src/dps8/dps8_ins.c                 cpu.PR[n].RNR = max3 (Crr, cpu.SDW->R1, cpu.TPR.TRR);
TRR                28 src/dps8/dps8_mp.h     word3 TRR;
TRR              4090 src/dps8/dps8_sys.c     { "cpus[].TPR.TRR",         SYM_STRUCT_OFFSET, SYM_UINT8_3,   offsetof (struct tpr_s,          TRR)         },
TRR               432 src/dps8/panelScraper.c                 SETL (bank_a,  0+3,  cpu.TPR.TRR, 3);
TRR               817 src/dps8/panelScraper.c