switches 1563 src/dps8/dps8_addrmods.c cpu.TPR.CA == cpu.switches.addr_switches)) switches 188 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.FLT_BASE); switches 190 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.cpu_num); switches 192 src/dps8/dps8_cpu.c (unsigned long long)cpus[cpu_unit_idx].switches.data_switches); switches 194 src/dps8/dps8_cpu.c PBI_64((unsigned long long)cpus[cpu_unit_idx].switches.data_switches)); switches 198 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches); switches 200 src/dps8/dps8_cpu.c PBI_32(cpus[cpu_unit_idx].switches.addr_switches)); switches 206 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); switches 208 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.init_enable [i]); switches 210 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.assignment [i]); switches 212 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.interlace [i]); switches 214 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.store_size [i]); switches 217 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode == \ switches 218 src/dps8/dps8_cpu.c procModeMultics ? "Multics" : cpus[cpu_unit_idx].switches.procMode == procModeGCOS ? "GCOS" : "???", switches 219 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode); switches 221 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable_cache ? "Enabled" : "Disabled"); switches 223 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.sdwam_enable ? "Enabled" : "Disabled"); switches 225 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.ptwam_enable ? "Enabled" : "Disabled"); switches 515 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.FLT_BASE = (uint) v; switches 517 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.cpu_num = (uint) v; switches 519 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = (word36) v; switches 533 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = d; switches 536 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches = (word18) v; switches 538 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.procMode = v ? procModeMultics : procModeGCOS; switches 549 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [port_num] = (uint) v; switches 551 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [port_num] = (uint) v; switches 553 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; switches 555 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [port_num] = (uint) v; switches 582 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [port_num] = (uint) v; switches 585 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable_cache = (uint) v ? true : false; switches 587 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.sdwam_enable = (uint) v ? true : false; switches 589 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.ptwam_enable = (uint) v ? true : false; switches 640 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].isolts_switches_save = cpus[cpu_unit_idx].switches; switches 642 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.data_switches = 00000030714000; switches 643 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.addr_switches = 0100150; switches 646 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [0] = 0; switches 647 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [0] = false; switches 648 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; switches 649 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [0] = false; switches 650 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [0] = store_sz; switches 652 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [1] = 0; switches 653 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [1] = false; switches 654 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; switches 655 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [1] = false; switches 656 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [1] = store_sz; switches 658 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [2] = 0; switches 659 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [2] = false; switches 660 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; switches 661 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [2] = false; switches 662 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [2] = store_sz; switches 664 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [3] = 0; switches 665 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [3] = false; switches 666 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; switches 667 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [3] = false; switches 668 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [3] = store_sz; switches 671 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [4] = 0; switches 672 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [4] = false; switches 673 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; switches 674 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [4] = false; switches 675 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [4] = 3; switches 677 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [5] = 0; switches 678 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [5] = false; switches 679 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; switches 680 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [5] = false; switches 681 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [5] = 3; switches 683 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [6] = 0; switches 684 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [6] = false; switches 685 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; switches 686 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [6] = false; switches 687 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [6] = 3; switches 689 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.assignment [7] = 0; switches 690 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [7] = false; switches 691 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; switches 692 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.init_enable [7] = false; switches 693 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.store_size [7] = 3; switches 695 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; //-V1048 switches 711 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches = cpus[cpu_unit_idx].isolts_switches_save; switches 872 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = port_num; switches 873 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 874 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 2; switches 875 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; switches 876 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 1; switches 879 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = 0; switches 880 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 881 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 0; switches 882 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; switches 883 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 0; switches 897 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = port_num; switches 898 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 899 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 7; switches 900 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; switches 901 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 1; switches 904 src/dps8/dps8_cpu.c cpun->switches.assignment[port_num] = 0; switches 905 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; switches 906 src/dps8/dps8_cpu.c cpun->switches.store_size[port_num] = 0; switches 907 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; switches 908 src/dps8/dps8_cpu.c cpun->switches.init_enable[port_num] = 0; switches 998 src/dps8/dps8_cpu.c cpu.cu.SD_ON = cpu.switches.sdwam_enable ? 1 : 0; switches 999 src/dps8/dps8_cpu.c cpu.cu.PT_ON = cpu.switches.ptwam_enable ? 1 : 0; switches 1357 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) switches 1362 src/dps8/dps8_cpu.c uint store_size = cpu.switches.store_size [port_num]; switches 1371 src/dps8/dps8_cpu.c uint base_addr_bks = (sz_wds * cpu.switches.assignment[port_num]) / SCBANK_SZ; switches 1419 src/dps8/dps8_cpu.c uint base_wds = sz_wds * cpu.switches.assignment[port_num]; switches 1787 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) switches 1789 src/dps8/dps8_cpu.c uint store_size = cpu.switches.store_size [port_num]; switches 1798 src/dps8/dps8_cpu.c uint base = sz_wds * cpu.switches.assignment[port_num]; switches 1836 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) switches 1848 src/dps8/dps8_cpu.c uint store_size = cpu.switches.store_size [port_num]; switches 1878 src/dps8/dps8_cpu.c uint base_addr_wds = sz_wds * cpu.switches.assignment[port_num]; switches 1960 src/dps8/dps8_cpu.c if (cpu.switches.serno) switches 1962 src/dps8/dps8_cpu.c cpu.switches.serno = sn; switches 1965 src/dps8/dps8_cpu.c sim_msg ("%s CPU serial number: %u\r\n", sim_name, cpu.switches.serno); switches 1973 src/dps8/dps8_cpu.c if (cpus[cpun].switches.serno) switches 1975 src/dps8/dps8_cpu.c cpus[cpun].switches.serno = sn; switches 1979 src/dps8/dps8_cpu.c sim_name, cpun, cpus[cpun].switches.serno); switches 2427 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.switches.data_switches; switches 4189 src/dps8/dps8_cpu.c uint fltAddress = (cpu.switches.FLT_BASE << 5) & 07740; switches 4211 src/dps8/dps8_cpu.c bool switches = cpu.execSwitches; switches 4212 src/dps8/dps8_cpu.c word36 sw = cpu.switches.data_switches; switches 4214 src/dps8/dps8_cpu.c if (switches && ((sw >> 8) & 01777) == (0717u << 1)) switches 4217 src/dps8/dps8_cpu.c switches = false; switches 4219 src/dps8/dps8_cpu.c if (switches) switches 5696 src/dps8/dps8_cpu.c putbits36_3 (& rsw2, 33, cpus[cpuNo].switches.cpu_num & 07LL); switches 5706 src/dps8/dps8_cpu.c (void)sprintf (serial, "%-11u", cpus[cpuNo].switches.serno); switches 6227 src/dps8/dps8_cpu.c cpus[i].switches.FLT_BASE = 2; // Some of the UnitTests assume this switches 1671 src/dps8/dps8_cpu.h switches_t switches; switches 435 src/dps8/dps8_ins.c putbits36_3 (& words[2], 27, (word3) cpu.switches.cpu_num); switches 3639 src/dps8/dps8_ins.c if (cpu.switches.procMode == procModeGCOS) switches 8377 src/dps8/dps8_ins.c cpu.rA = cpu.switches.data_switches; switches 8408 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [0] & 07LL) switches 8410 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) switches 8412 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [0] & 01LL) switches 8414 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] ? 1LL:0LL) switches 8416 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [0] & 07LL) switches 8419 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [1] & 07LL) switches 8421 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) switches 8423 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [1] & 01LL) switches 8425 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] ? 1LL:0LL) switches 8427 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [1] & 07LL) switches 8430 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [2] & 07LL) switches 8432 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) switches 8434 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [2] & 01LL) switches 8436 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] ? 1LL:0LL) switches 8438 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [2] & 07LL) switches 8441 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [3] & 07LL) switches 8443 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) switches 8445 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [3] & 01LL) switches 8447 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] ? 1LL:0LL) switches 8449 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [3] & 07LL) switches 8522 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[0] == 2 ? switches 8524 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[1] == 2 ? switches 8526 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[2] == 2 ? switches 8528 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[3] == 2 ? switches 8540 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.FLT_BASE & 0177LL) switches 8565 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.enable_cache ? 1 : 0) switches 8576 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.procMode == procModeMultics ? 1LL : 0LL) switches 8598 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.cpu_num & 07LL) switches 8635 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [4] & 07LL) switches 8637 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) switches 8639 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [4] & 01LL) switches 8641 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] ? 1LL:0LL) switches 8643 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [4] & 07LL) switches 8646 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [5] & 07LL) switches 8648 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) switches 8650 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [5] & 01LL) switches 8652 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] ? 1LL:0LL) switches 8654 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [5] & 07LL) switches 8657 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [6] & 07LL) switches 8659 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) switches 8661 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [6] & 01LL) switches 8663 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] ? 1LL:0LL) switches 8665 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [6] & 07LL) switches 8668 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [7] & 07LL) switches 8670 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL) switches 8672 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [7] & 01LL) switches 8674 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] ? 1LL:0LL) switches 8676 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [7] & 07LL) switches 8697 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] == 2 ? switches 8699 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] == 2 ? switches 8701 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] == 2 ? switches 8703 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] == 2 ? switches 8706 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] == 2 ? switches 8708 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] == 2 ? switches 8710 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] == 2 ? switches 8712 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] == 2 ? switches 10089 src/dps8/dps8_ins.c if (! cpu.switches.enable [port_num] || switches 10092 src/dps8/dps8_ins.c uint store_size = cpu.switches.store_size [port_num]; switches 10095 src/dps8/dps8_ins.c uint base = sz_wds * cpu.switches.assignment[port_num]; switches 428 src/dps8/panelScraper.c SETL (bank_a, 27+3, (word3) cpu.switches.cpu_num, 3); switches 1396 src/dps8/panelScraper.c SETS (cpu.switches.data_switches, port_data, 0, 36); switches 1400 src/dps8/panelScraper.c SETS (cpu.switches.addr_switches, port_data, 0, 18); switches 9913 src/simh/scp.c t_stat sim_exp_set (EXPECT *exp, const char *match, int32 cnt, uint32 after, int32 switches, const char *act) switches 9924 src/simh/scp.c if (switches & EXP_TYP_REGEX) { switches 9929 src/simh/scp.c if (switches & EXP_TYP_REGEX_I) { switches 9942 src/simh/scp.c (exp->rules[i].switches & EXP_TYP_PERSIST)) switches 9968 src/simh/scp.c ep->switches = switches; /* set switches */ switches 9975 src/simh/scp.c if (switches & EXP_TYP_REGEX) { switches 10013 src/simh/scp.c size_t compare_size = (exp->rules[i].switches & EXP_TYP_REGEX) ? MAX(10 * strlen(ep->match_pattern), 1024) : exp->rules[i].size; switches 10029 src/simh/scp.c if (ep->switches & EXP_TYP_PERSIST) switches 10031 src/simh/scp.c if (ep->switches & EXP_TYP_CLEARALL) switches 10033 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX) switches 10035 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX_I) switches 10114 src/simh/scp.c if (ep->switches & EXP_TYP_REGEX) { switches 10182 src/simh/scp.c int32 switches = ep->switches; switches 10190 src/simh/scp.c if (ep->switches & EXP_TYP_CLEARALL) /* Clear-all expect rule? */ switches 10193 src/simh/scp.c if (!(ep->switches & EXP_TYP_PERSIST)) /* One shot expect rule? */ switches 10197 src/simh/scp.c (switches & EXP_TYP_TIME) ? switches 189 src/simh/scp.h t_stat sim_exp_set (EXPECT *exp, const char *match, int32 cnt, uint32 after, int32 switches, const char *act); switches 633 src/simh/scp.h const char *switches, switches 630 src/simh/sim_defs.h int32 switches; /* flags */