reg               321 src/dps8/dps8_eis.c static word36 getCrAR (cpu_state_t * cpup, word4 reg)
reg               323 src/dps8/dps8_eis.c     if (reg == 0)
reg               326 src/dps8/dps8_eis.c     if (reg & 010) /* Xn */
reg               327 src/dps8/dps8_eis.c       return cpu.rX [X (reg)];
reg               329 src/dps8/dps8_eis.c     switch (reg)
reg              1287 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1289 src/dps8/dps8_eis.c         address += getMFReg18 (cpup, reg, false, true, mod_fault); // ID=1: disallow du, allow n,ic
reg              1439 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1441 src/dps8/dps8_eis.c         e -> N [k - 1] = (uint) getMFReg36 (cpup, reg, false, false, mod_fault); // RL=1: disallow du,n,ic
reg              1732 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1733 src/dps8/dps8_eis.c         e->N[k-1] = getMFReg18 (cpup,reg, false, false, mod_fault) & 077; // RL=1: disallow du,n,ic
reg              1906 src/dps8/dps8_eis.c         uint reg = opDesc & 017;
reg              1907 src/dps8/dps8_eis.c         e->N[k-1] = getMFReg36(cpup, reg, false, false, mod_fault) & 077777777;  // RL=1: disallow du,n,ic
reg              1908 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\r\n", k, reg, (word36)e->N[k-1]);
reg              2074 src/dps8/dps8_eis.c     word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              2077 src/dps8/dps8_eis.c     word36 ur = getCrAR (cpup, reg);
reg              2155 src/dps8/dps8_eis.c     word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              2158 src/dps8/dps8_eis.c     word36 ur = getCrAR (cpup, reg);
reg              2202 src/dps8/dps8_eis.c     word6 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              2205 src/dps8/dps8_eis.c     word36 rcnt = getCrAR (cpup, reg);
reg              2221 src/dps8/dps8_eis.c                sz, ARn, address, reg, r);
reg              2283 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2285 src/dps8/dps8_eis.c     word24 r = getCrAR (cpup, (word4) reg) & MASK24;
reg              2349 src/dps8/dps8_eis.c 
reg              2352 src/dps8/dps8_eis.c 
reg              2492 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2495 src/dps8/dps8_eis.c     int32_t r = (int32_t) (getCrAR (cpup, reg) & MASK18);
reg              2500 src/dps8/dps8_eis.c                ARn, address, reg, r);
reg              2537 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2539 src/dps8/dps8_eis.c     word24 r = getCrAR (cpup, (word4) reg) & MASK24;
reg              2575 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2578 src/dps8/dps8_eis.c     int32_t r = (int32_t) (getCrAR (cpup, reg) & MASK18);
reg              2583 src/dps8/dps8_eis.c                ARn, address, reg, r);
reg              2621 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB);
reg              2624 src/dps8/dps8_eis.c     word21 r = getCrAR (cpup, reg) & MASK21;;
reg              2628 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\r\n", ARn, address, reg, r);
reg              2904 src/dps8/dps8_eis.c     word4 reg = (word4) GET_TD (cpu.cu.IWB); // 4-bit register modification (None except
reg              2912 src/dps8/dps8_eis.c     word36 rcnt = getCrAR (cpup, reg);
reg              2930 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\r\n", sz, ARn, address, reg, r);
reg              7872 src/dps8/dps8_ins.c                     uint reg = cpu.tweaks.l68_mode ? L68_APU_HIST_REG : DPS8M_APU_HIST_REG;
reg              7873 src/dps8/dps8_ins.c                     cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0];
reg              7874 src/dps8/dps8_ins.c                     cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1];
reg              7875 src/dps8/dps8_ins.c                     cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE;
reg              7926 src/dps8/dps8_ins.c                     uint reg = cpu.tweaks.l68_mode ? L68_DU_HIST_REG : DPS8M_EAPU_HIST_REG;
reg              7927 src/dps8/dps8_ins.c                     cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0];
reg              7928 src/dps8/dps8_ins.c                     cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1];
reg              7929 src/dps8/dps8_ins.c                     cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE;
reg              7948 src/dps8/dps8_ins.c                     uint reg = cpu.tweaks.l68_mode ? L68_OU_HIST_REG : DPS8M_DU_OU_HIST_REG;
reg              7949 src/dps8/dps8_ins.c                     cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0];
reg              7950 src/dps8/dps8_ins.c                     cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1];
reg              7951 src/dps8/dps8_ins.c                     cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE;
reg                98 src/dps8/hdbg.c     } reg;
reg               277 src/dps8/hdbg.c   hevp[p].reg.type = type;
reg               278 src/dps8/hdbg.c   hevp[p].reg.data = data;
reg               285 src/dps8/hdbg.c   hevp[p].reg.type = type;
reg               286 src/dps8/hdbg.c   hevp[p].reg.data = data;
reg               433 src/dps8/hdbg.c   if (p->reg.type == hreg_IR)
reg               439 src/dps8/hdbg.c                    regNames[p->reg.type],
reg               440 src/dps8/hdbg.c                    (unsigned long long int)p->reg.data,
reg               441 src/dps8/hdbg.c                    TSTF (p->reg.data, I_ZERO),
reg               442 src/dps8/hdbg.c                    TSTF (p->reg.data, I_NEG),
reg               443 src/dps8/hdbg.c                    TSTF (p->reg.data, I_CARRY),
reg               444 src/dps8/hdbg.c                    TSTF (p->reg.data, I_OFLOW),
reg               445 src/dps8/hdbg.c                    TSTF (p->reg.data, I_TALLY));
reg               446 src/dps8/hdbg.c   else if (p->reg.type >= hreg_X0 && p->reg.type <= hreg_X7)
reg               452 src/dps8/hdbg.c                    regNames[p->reg.type],
reg               453 src/dps8/hdbg.c                    (unsigned long long int)p->reg.data);
reg               460 src/dps8/hdbg.c                    regNames[p->reg.type],
reg               461 src/dps8/hdbg.c                    (unsigned long long int)p->reg.data);
reg               466 src/dps8/hdbg.c   if (p->reg.type >= hreg_PR0 && p->reg.type <= hreg_PR7)
reg               472 src/dps8/hdbg.c                     regNames[p->reg.type],
reg               482 src/dps8/hdbg.c                    regNames[p->reg.type],
reg               496 src/dps8/hdbg.c                  regNames[p->reg.type],
reg               942 src/libsir/src/sirinternal.c     DWORD reg = EventRegister(&SIR_EVENTLOG_GUID, NULL, NULL,
reg               944 src/libsir/src/sirinternal.c     if (ERROR_SUCCESS == reg) {
reg               948 src/libsir/src/sirinternal.c         _sir_selflog("failed to open eventlog! error: %lu", reg);
reg               949 src/libsir/src/sirinternal.c         (void)_sir_handlewin32err(reg);