rRALR             127 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.rRALR) {
rRALR             356 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.rRALR == 0)
rRALR             360 src/dps8/doAppendCycleInstructionFetch.h   if (! (cpu.PPR.PRR < cpu.rRALR)) {
rRALR             362 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\r\n", cpu.PPR.PRR, cpu.rRALR);
rRALR             118 src/dps8/doAppendCycleOperandRead.h     if (cpu.rRALR && (cpu.PPR.PRR >= cpu.rRALR)) {
rRALR             360 src/dps8/doAppendCycleOperandRead.h   if (cpu.rRALR == 0)
rRALR             364 src/dps8/doAppendCycleOperandRead.h   if (! (cpu.PPR.PRR < cpu.rRALR)) {
rRALR             366 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\r\n", cpu.PPR.PRR, cpu.rRALR);
rRALR            1576 src/dps8/dps8_append.c     if (cpu.rRALR == 0)
rRALR            1580 src/dps8/dps8_append.c     if (! (cpu.PPR.PRR < cpu.rRALR))
rRALR            1584 src/dps8/dps8_append.c                 cpu.PPR.PRR, cpu.rRALR);
rRALR            1809 src/dps8/dps8_cpu.h     word3    rRALR;    // ring alarm [3b] [map: 33 0's, RALR]
rRALR            3911 src/dps8/dps8_ins.c             cpu.Yblock8[7] = (((-- cpu.shadowTR) & MASK27) << 9) | (cpu.rRALR & 07);
rRALR            3913 src/dps8/dps8_ins.c             cpu.Yblock8[7] = ((cpu.rTR & MASK27) << 9) | (cpu.rRALR & 07);
rRALR            7472 src/dps8/dps8_ins.c             cpu.CY = (word36)cpu.rRALR;
rRALR            7775 src/dps8/dps8_ins.c             cpu.rRALR = cpu.CY & MASK3;
rRALR            7776 src/dps8/dps8_ins.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\r\n", cpu.rRALR);
rRALR            7781 src/dps8/dps8_ins.c  sim_printf (" RALR set to %o  PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC);
rRALR            4121 src/dps8/dps8_sys.c     { "cpus[].rRALR",           SYM_STRUCT_OFFSET, SYM_UINT8_3,   offsetof (cpu_state_t,           rRALR)       },
rRALR             321 src/dps8/panelScraper.c                 SETL (bank_a, 24+3, cpu.rRALR, 3);