reg 321 src/dps8/dps8_eis.c static word36 getCrAR (cpu_state_t * cpup, word4 reg) reg 323 src/dps8/dps8_eis.c if (reg == 0) reg 326 src/dps8/dps8_eis.c if (reg & 010) /* Xn */ reg 327 src/dps8/dps8_eis.c return cpu.rX [X (reg)]; reg 329 src/dps8/dps8_eis.c switch (reg) reg 1287 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1289 src/dps8/dps8_eis.c address += getMFReg18 (cpup, reg, false, true, mod_fault); // ID=1: disallow du, allow n,ic reg 1433 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1435 src/dps8/dps8_eis.c e -> N [k - 1] = (uint) getMFReg36 (cpup, reg, false, false, mod_fault); // RL=1: disallow du,n,ic reg 1707 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1708 src/dps8/dps8_eis.c e->N[k-1] = getMFReg18 (cpup,reg, false, false, mod_fault) & 077; // RL=1: disallow du,n,ic reg 1874 src/dps8/dps8_eis.c uint reg = opDesc & 017; reg 1875 src/dps8/dps8_eis.c e->N[k-1] = getMFReg36(cpup, reg, false, false, mod_fault) & 077777777; // RL=1: disallow du,n,ic reg 1876 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]); reg 1964 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 1967 src/dps8/dps8_eis.c word36 ur = getCrAR (cpup, reg); reg 2045 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 2048 src/dps8/dps8_eis.c word36 ur = getCrAR (cpup, reg); reg 2092 src/dps8/dps8_eis.c word6 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 2095 src/dps8/dps8_eis.c word36 rcnt = getCrAR (cpup, reg); reg 2111 src/dps8/dps8_eis.c sz, ARn, address, reg, r); reg 2173 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2175 src/dps8/dps8_eis.c word24 r = getCrAR (cpup, (word4) reg) & MASK24; reg 2239 src/dps8/dps8_eis.c reg 2242 src/dps8/dps8_eis.c reg 2382 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2385 src/dps8/dps8_eis.c int32_t r = (int32_t) (getCrAR (cpup, reg) & MASK18); reg 2390 src/dps8/dps8_eis.c ARn, address, reg, r); reg 2427 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2429 src/dps8/dps8_eis.c word24 r = getCrAR (cpup, (word4) reg) & MASK24; reg 2465 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2468 src/dps8/dps8_eis.c int32_t r = (int32_t) (getCrAR (cpup, reg) & MASK18); reg 2473 src/dps8/dps8_eis.c ARn, address, reg, r); reg 2511 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); reg 2514 src/dps8/dps8_eis.c word21 r = getCrAR (cpup, reg) & MASK21;; reg 2518 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); reg 2794 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); // 4-bit register modification (None except reg 2802 src/dps8/dps8_eis.c word36 rcnt = getCrAR (cpup, reg); reg 2820 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); reg 7679 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_APU_HIST_REG : DPS8M_APU_HIST_REG; reg 7680 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; reg 7681 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; reg 7682 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; reg 7727 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_DU_HIST_REG : DPS8M_EAPU_HIST_REG; reg 7728 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; reg 7729 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; reg 7730 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; reg 7749 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_OU_HIST_REG : DPS8M_DU_OU_HIST_REG; reg 7750 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; reg 7751 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; reg 7752 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; reg 97 src/dps8/hdbg.c } reg; reg 269 src/dps8/hdbg.c hevents[p].reg.type = type; reg 270 src/dps8/hdbg.c hevents[p].reg.data = data; reg 277 src/dps8/hdbg.c hevents[p].reg.type = type; reg 278 src/dps8/hdbg.c hevents[p].reg.data = data; reg 425 src/dps8/hdbg.c if (p->reg.type == hreg_IR) reg 431 src/dps8/hdbg.c regNames[p->reg.type], reg 432 src/dps8/hdbg.c (unsigned long long int)p->reg.data, reg 433 src/dps8/hdbg.c TSTF (p->reg.data, I_ZERO), reg 434 src/dps8/hdbg.c TSTF (p->reg.data, I_NEG), reg 435 src/dps8/hdbg.c TSTF (p->reg.data, I_CARRY), reg 436 src/dps8/hdbg.c TSTF (p->reg.data, I_OFLOW), reg 437 src/dps8/hdbg.c TSTF (p->reg.data, I_TALLY)); reg 438 src/dps8/hdbg.c else if (p->reg.type >= hreg_X0 && p->reg.type <= hreg_X7) reg 444 src/dps8/hdbg.c regNames[p->reg.type], reg 445 src/dps8/hdbg.c (unsigned long long int)p->reg.data); reg 452 src/dps8/hdbg.c regNames[p->reg.type], reg 453 src/dps8/hdbg.c (unsigned long long int)p->reg.data); reg 458 src/dps8/hdbg.c if (p->reg.type >= hreg_PR0 && p->reg.type <= hreg_PR7) reg 464 src/dps8/hdbg.c regNames[p->reg.type], reg 474 src/dps8/hdbg.c regNames[p->reg.type], reg 488 src/dps8/hdbg.c regNames[p->reg.type], reg 941 src/libsir/src/sirinternal.c DWORD reg = EventRegister(&SIR_EVENTLOG_GUID, NULL, NULL, reg 943 src/libsir/src/sirinternal.c if (ERROR_SUCCESS == reg) { reg 947 src/libsir/src/sirinternal.c _sir_selflog("failed to open eventlog! error: %lu", reg); reg 948 src/libsir/src/sirinternal.c (void)_sir_handlewin32err(reg);