rRALR 122 src/dps8/doAppendCycleInstructionFetch.h if (cpu.rRALR) { rRALR 348 src/dps8/doAppendCycleInstructionFetch.h if (cpu.rRALR == 0) rRALR 352 src/dps8/doAppendCycleInstructionFetch.h if (! (cpu.PPR.PRR < cpu.rRALR)) { rRALR 354 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR); rRALR 118 src/dps8/doAppendCycleOperandRead.h if (cpu.rRALR && (cpu.PPR.PRR >= cpu.rRALR)) { rRALR 358 src/dps8/doAppendCycleOperandRead.h if (cpu.rRALR == 0) rRALR 362 src/dps8/doAppendCycleOperandRead.h if (! (cpu.PPR.PRR < cpu.rRALR)) { rRALR 364 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR); rRALR 1562 src/dps8/dps8_append.c if (cpu.rRALR == 0) rRALR 1566 src/dps8/dps8_append.c if (! (cpu.PPR.PRR < cpu.rRALR)) rRALR 1570 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.rRALR); rRALR 1758 src/dps8/dps8_cpu.h word3 rRALR; // ring alarm [3b] [map: 33 0's, RALR] rRALR 3837 src/dps8/dps8_ins.c cpu.Yblock8[7] = (((-- cpu.shadowTR) & MASK27) << 9) | (cpu.rRALR & 07); rRALR 3839 src/dps8/dps8_ins.c cpu.Yblock8[7] = ((cpu.rTR & MASK27) << 9) | (cpu.rRALR & 07); rRALR 7317 src/dps8/dps8_ins.c cpu.CY = (word36)cpu.rRALR; rRALR 7609 src/dps8/dps8_ins.c cpu.rRALR = cpu.CY & MASK3; rRALR 7610 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\n", cpu.rRALR); rRALR 7615 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); rRALR 4076 src/dps8/dps8_sys.c { "cpus[].rRALR", SYM_STRUCT_OFFSET, SYM_UINT8_3, offsetof (cpu_state_t, rRALR) }, rRALR 327 src/dps8/panelScraper.c SETL (bank_a, 24+3, cpu.rRALR, 3);