IC                280 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                347 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                298 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                300 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                469 src/dps8/doAppendCycleIndirectWordFetch.h           cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                635 src/dps8/doAppendCycleInstructionFetch.h   cpu.PPR.IC = cpu.TPR.CA;
IC                658 src/dps8/doAppendCycleInstructionFetch.h           cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                351 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                742 src/dps8/doAppendCycleOperandRead.h     cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18;
IC                755 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.IC = cpu.TPR.CA;
IC                802 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.IC = cpu.TPR.CA;
IC                813 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                303 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                366 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.PPR.IC = cpu.TPR.CA;
IC                390 src/dps8/doAppendCycleRTCDOperandFetch.h           cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                 84 src/dps8/dps8_addrmods.c           return cpu.PPR.IC;
IC               2063 src/dps8/dps8_append.c         cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18;
IC               2112 src/dps8/dps8_append.c     cpu.PPR.IC    = cpu.TPR.CA;
IC               2166 src/dps8/dps8_append.c     cpu.PPR.IC    = cpu.TPR.CA;
IC               2212 src/dps8/dps8_append.c             cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC                963 src/dps8/dps8_cpu.c     cpu.PPR.IC   = 0;
IC               1663 src/dps8/dps8_cpu.c     { ORDATA (IC, dummy_IC,       VASIZE), 0, 0, 0 },
IC               1665 src/dps8/dps8_cpu.c     { ORDATA (IC, cpus[0].PPR.IC, VASIZE), 0, 0, 0 },
IC               1799 src/dps8/dps8_cpu.c         sim_brk_test ((cpu.PPR.IC & 0777777) |
IC               2241 src/dps8/dps8_cpu.c     cpus [0].PPR.IC = dummy_IC;
IC               2676 src/dps8/dps8_cpu.c                     get_BAR_address (cpup, cpu.PPR.IC);
IC               2699 src/dps8/dps8_cpu.c                         (cpu.PPR.IC & 1) == 0 &&
IC               2716 src/dps8/dps8_cpu.c                     if ((cpu.PPR.IC & 1) == 1)
IC               2869 src/dps8/dps8_cpu.c                 fetchInstruction (cpup, cpu.PPR.IC);
IC               2888 src/dps8/dps8_cpu.c                           stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC)
IC               3168 src/dps8/dps8_cpu.c                    (cpu.cu.rd && (cpu.PPR.IC & 1)) ||
IC               3173 src/dps8/dps8_cpu.c                     -- cpu.PPR.IC;
IC               3194 src/dps8/dps8_cpu.c                   cpu.PPR.IC  += ci->info->ndes;
IC               3195 src/dps8/dps8_cpu.c                   cpu.PPR.IC ++;
IC               3241 src/dps8/dps8_cpu.c                   cpu.PPR.IC ++;
IC               3243 src/dps8/dps8_cpu.c                     cpu.PPR.IC     += ci->info->ndes;
IC               3266 src/dps8/dps8_cpu.c               if ((cpu.PPR.IC & 1) == 0 &&
IC               3270 src/dps8/dps8_cpu.c                   (cpu.PPR.IC & ~3u) != (cpu.last_write  & ~3u))
IC               3272 src/dps8/dps8_cpu.c                   cpu.PPR.IC ++;
IC               3279 src/dps8/dps8_cpu.c               cpu.PPR.IC ++;
IC               3281 src/dps8/dps8_cpu.c                 cpu.PPR.IC += ci->info->ndes;
IC               3296 src/dps8/dps8_cpu.c               cpu.PPR.IC += ci->info->ndes;
IC               3297 src/dps8/dps8_cpu.c               cpu.PPR.IC ++;
IC               3514 src/dps8/dps8_cpu.c     dummy_IC = cpu.PPR.IC;
IC               3730 src/dps8/dps8_cpu.c                    addr, cpu.PPR.PSR, cpu.PPR.IC, ctx);
IC               3737 src/dps8/dps8_cpu.c                     (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr,
IC               3769 src/dps8/dps8_cpu.c                 cpu.PPR.PSR, cpu.PPR.IC);
IC               3812 src/dps8/dps8_cpu.c                  (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC,
IC               3834 src/dps8/dps8_cpu.c                   cpu.PPR.PSR, cpu.PPR.IC);
IC               3850 src/dps8/dps8_cpu.c                 cpu.PPR.PSR,     cpu.PPR.IC);
IC               3892 src/dps8/dps8_cpu.c                 (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC,
IC               3928 src/dps8/dps8_cpu.c                    addr, cpu.PPR.PSR, cpu.PPR.IC, ctx);
IC               3935 src/dps8/dps8_cpu.c                  (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC,
IC               3946 src/dps8/dps8_cpu.c                 cpu.PPR.PSR, cpu.PPR.IC);
IC               3965 src/dps8/dps8_cpu.c                     addr, cpu.PPR.PSR, cpu.PPR.IC, ctx);
IC               3972 src/dps8/dps8_cpu.c                  (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC,
IC               3983 src/dps8/dps8_cpu.c                 cpu.PPR.PSR, cpu.PPR.IC);
IC               4022 src/dps8/dps8_cpu.c              (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC,
IC               4045 src/dps8/dps8_cpu.c              (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC,
IC               4557 src/dps8/dps8_cpu.c     putbits36_18 (& w1,      54 - 36, cpu.PPR.IC);
IC                100 src/dps8/dps8_cpu.h     word18  IC;  // The word offset from the origin of the procedure segment
IC               1033 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0))
IC               1679 src/dps8/dps8_cpu.h         word18 IC;
IC                347 src/dps8/dps8_eis.c           return cpu.PPR.IC;
IC                444 src/dps8/dps8_eis.c           return cpu.PPR.IC;
IC                519 src/dps8/dps8_eis.c           return cpu.PPR.IC;
IC                380 src/dps8/dps8_faults.c  sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC);
IC                385 src/dps8/dps8_faults.c  sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC);
IC                417 src/dps8/dps8_faults.c     fault_ic  = cpu . PPR.IC;
IC                689 src/dps8/dps8_faults.c                      cpu.PPR.IC);
IC                835 src/dps8/dps8_faults.c                      cpu.PPR.IC);
IC                135 src/dps8/dps8_iefp.c                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
IC                210 src/dps8/dps8_iefp.c         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
IC                281 src/dps8/dps8_iefp.c         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
IC                352 src/dps8/dps8_iefp.c         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
IC                422 src/dps8/dps8_iefp.c         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
IC                494 src/dps8/dps8_iefp.c         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
IC                564 src/dps8/dps8_iefp.c         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
IC               1154 src/dps8/dps8_iefp.c                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
IC               1279 src/dps8/dps8_iefp.c                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
IC                312 src/dps8/dps8_ins.c             cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18;
IC                318 src/dps8/dps8_ins.c         cpu.PPR.IC = cpu.TPR.CA;
IC                323 src/dps8/dps8_ins.c                __func__, cpu.PPR.PSR, cpu.PPR.IC);
IC                324 src/dps8/dps8_ins.c     if (cpu.PPR.IC & 1)
IC                437 src/dps8/dps8_ins.c     putbits36_18 (& words[4],  0, cpu.PPR.IC);
IC                606 src/dps8/dps8_ins.c     cpu.cu_data.IC  = cpu.PPR.IC;
IC                716 src/dps8/dps8_ins.c     cpu.PPR.IC          = getbits36_18 (words[4], 0);
IC               1158 src/dps8/dps8_ins.c     if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0))
IC               1194 src/dps8/dps8_ins.c         if ((cpu.PPR.IC & 1) == 0) // Even
IC               1222 src/dps8/dps8_ins.c         char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname,
IC               1232 src/dps8/dps8_ins.c                                cpu.BAR.BASE, cpu.PPR.IC, where);
IC               1236 src/dps8/dps8_ins.c                     sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where);
IC               1245 src/dps8/dps8_ins.c                                cpu.BAR.BASE, cpu.PPR.IC, where);
IC               1250 src/dps8/dps8_ins.c                                cpu.PPR.PSR, cpu.PPR.IC, where);
IC               1264 src/dps8/dps8_ins.c                   cpu.PPR.IC,
IC               1281 src/dps8/dps8_ins.c                   cpu.PPR.IC,
IC               1303 src/dps8/dps8_ins.c                   cpu.PPR.IC,
IC               1321 src/dps8/dps8_ins.c                   cpu.PPR.IC,
IC               1373 src/dps8/dps8_ins.c   trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD);
IC               1531 src/dps8/dps8_ins.c       if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1))
IC               1538 src/dps8/dps8_ins.c     if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1))
IC               1739 src/dps8/dps8_ins.c     if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) {
IC               1832 src/dps8/dps8_ins.c                cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0],
IC               1844 src/dps8/dps8_ins.c       bool icOdd  = !! (cpu.PPR.IC & 1);
IC               1915 src/dps8/dps8_ins.c             word18 saveIC = cpu.PPR.IC;
IC               1917 src/dps8/dps8_ins.c             ReadInstructionFetch (cpup, cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]);
IC               1918 src/dps8/dps8_ins.c             cpu.PPR.IC = saveIC;
IC               2085 src/dps8/dps8_ins.c   bool icOdd = !! (cpu.PPR.IC & 1);
IC               2316 src/dps8/dps8_ins.c                cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
IC               2987 src/dps8/dps8_ins.c             word18 ret = (cpu.PPR.IC + 1) & MASK18;
IC               3928 src/dps8/dps8_ins.c           SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18);
IC               3941 src/dps8/dps8_ins.c           cpu.CY      = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18;
IC               4012 src/dps8/dps8_ins.c               putbits36_18 (& cpu.Ypair[1],  0, cpu.PPR.IC + 2);
IC               4022 src/dps8/dps8_ins.c               putbits36_18 (& cpu.Ypair[1],  0, cpu.cu_data.IC + 2);
IC               6474 src/dps8/dps8_ins.c             cpu.PPR.IC = GETHI (cpu.CY);
IC               7261 src/dps8/dps8_ins.c             if ((cpu.PPR.IC & 1) == 0)
IC               7564 src/dps8/dps8_ins.c  sim_printf (" ldt %d  PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC);
IC               7615 src/dps8/dps8_ins.c  sim_printf (" RALR set to %o  PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC);
IC               8680 src/dps8/dps8_ins.c           if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) {
IC               8714 src/dps8/dps8_ins.c                           " no events in queue\n", cpu.PPR.IC);
IC               8731 src/dps8/dps8_ins.c           if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012)
IC               8774 src/dps8/dps8_ins.c 
IC               8784 src/dps8/dps8_ins.c               (cpu.PPR.PSR != 0 || cpu.PPR.IC != 0)) {
IC               8786 src/dps8/dps8_ins.c             sim_printf ("giveup DIS %o:%o\r\n", cpu.PPR.PSR, cpu.PPR.IC);
IC               8814 src/dps8/dps8_ins.c           if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535)
IC               9848 src/dps8/dps8_ins.c              (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC);
IC               3506 src/dps8/dps8_iom.c                __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC);
IC               2727 src/dps8/dps8_sys.c     word18 icOffset = cpu.PPR.IC;
IC               4058 src/dps8/dps8_sys.c     { "cpus[].PPR.IC",          SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct ppr_s,          IC)          },
IC                171 src/dps8/hdbg.c   if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \
IC                194 src/dps8/hdbg.c   hevents[p].trace.ic       = cpu.PPR.IC;
IC                663 src/dps8/panelScraper.c           SETL (bank_e, 0+3, cpu.PPR.IC, 18);
IC                923 src/dps8/panelScraper.c     SETL (bank_g,  0, cpu.PPR.IC, 18);
IC                957 src/dps8/panelScraper.c     SETL (bank_j, 3, cpu.PPR.IC, 18);