interlace 186 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.interlace [i]); interlace 529 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [port_num] = (uint) v; interlace 625 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [0] = false; interlace 631 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [1] = false; interlace 637 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [2] = false; interlace 643 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [3] = false; interlace 650 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [4] = false; interlace 656 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [5] = false; interlace 662 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [6] = false; interlace 668 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.interlace [7] = false; interlace 853 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; interlace 860 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; interlace 878 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; interlace 885 src/dps8/dps8_cpu.c cpun->switches.interlace[port_num] = 0; interlace 707 src/dps8/dps8_cpu.h uint interlace [N_CPU_PORTS]; // 0/2/4 interlace 8202 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] ? 1LL:0LL) interlace 8213 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] ? 1LL:0LL) interlace 8224 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] ? 1LL:0LL) interlace 8235 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] ? 1LL:0LL) interlace 8310 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[0] == 2 ? interlace 8312 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[1] == 2 ? interlace 8314 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[2] == 2 ? interlace 8316 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[3] == 2 ? interlace 8425 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] ? 1LL:0LL) interlace 8436 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] ? 1LL:0LL) interlace 8447 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] ? 1LL:0LL) interlace 8458 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] ? 1LL:0LL) interlace 8481 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] == 2 ? interlace 8483 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] == 2 ? interlace 8485 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] == 2 ? interlace 8487 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] == 2 ? interlace 8490 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] == 2 ? interlace 8492 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] == 2 ? interlace 8494 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] == 2 ? interlace 8496 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] == 2 ? interlace 595 src/dps8/dps8_scu.c uint interlace; // 1 bit interlace 677 src/dps8/dps8_scu.c sim_printf("Interlace: %o\n", scup -> interlace); interlace 929 src/dps8/dps8_scu.c sw -> interlace = (uint) v; interlace 1132 src/dps8/dps8_scu.c up -> interlace = sw -> interlace; interlace 1703 src/dps8/dps8_scu.c up -> interlace = (rega >> 5) & 1; interlace 2013 src/dps8/dps8_scu.c putbits36_1 (& a, 30, (word1) up -> interlace); interlace 49 src/dps8/dps8_scu.h uint interlace; // 1 bit