enable 199 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); enable 544 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; enable 637 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; enable 643 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 649 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; enable 655 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; enable 662 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; enable 668 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; enable 674 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; enable 680 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; enable 684 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; //-V1048 enable 864 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 871 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 889 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 896 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 1322 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) enable 710 src/dps8/dps8_cpu.h uint enable [N_CPU_PORTS]; enable 8267 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) enable 8278 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) enable 8289 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) enable 8300 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) enable 8490 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) enable 8501 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) enable 8512 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) enable 8523 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL)