evcnt 64 src/dps8/doAppendCycleInstructionFetch.h static int evcnt = 0; evcnt 66 src/dps8/doAppendCycleInstructionFetch.h (void)evcnt; evcnt 552 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 557 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 562 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 578 src/dps8/doAppendCycleInstructionFetch.h evcnt ++; evcnt 59 src/dps8/doAppendCycleOperandRead.h static int evcnt = 0; evcnt 61 src/dps8/doAppendCycleOperandRead.h (void)evcnt; evcnt 138 src/dps8/doAppendCycleOperandRead.h cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, evcnt 145 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 161 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 171 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 673 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 679 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 685 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); evcnt 694 src/dps8/doAppendCycleOperandRead.h evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); evcnt 697 src/dps8/doAppendCycleOperandRead.h evcnt ++;