enable 180 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); enable 530 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; enable 625 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; enable 631 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 637 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; enable 643 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; enable 650 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; enable 656 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; enable 662 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; enable 668 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; enable 672 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 852 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 859 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 877 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 884 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 1313 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) enable 708 src/dps8/dps8_cpu.h uint enable [N_CPU_PORTS]; enable 8198 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) enable 8209 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) enable 8220 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) enable 8231 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) enable 8421 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) enable 8432 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) enable 8443 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) enable 8454 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL)