enable 180 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); enable 531 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; enable 626 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; enable 632 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 638 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; enable 644 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; enable 651 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; enable 657 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; enable 663 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; enable 669 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; enable 673 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 855 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 862 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 880 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 887 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 1320 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) enable 708 src/dps8/dps8_cpu.h uint enable [N_CPU_PORTS]; enable 8198 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) enable 8209 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) enable 8220 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) enable 8231 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) enable 8421 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) enable 8432 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) enable 8443 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) enable 8454 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL)