enable 180 src/dps8/dps8_cpu.c 'A' + i, cpus[cpu_unit_idx].switches.enable [i]); enable 530 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [port_num] = (uint) v; enable 626 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [0] = false; enable 632 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 638 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [2] = false; enable 644 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [3] = false; enable 651 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [4] = false; enable 657 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [5] = false; enable 663 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [6] = false; enable 669 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [7] = false; enable 675 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].switches.enable [1] = true; enable 833 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 840 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 858 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 1; enable 865 src/dps8/dps8_cpu.c cpun->switches.enable[port_num] = 0; enable 1294 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) enable 705 src/dps8/dps8_cpu.h uint enable [N_CPU_PORTS]; enable 8197 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) enable 8208 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) enable 8219 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) enable 8230 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) enable 8420 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) enable 8431 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) enable 8442 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) enable 8453 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL)