csh2_on           185 src/dps8/dps8_cache.c   return (cpu.CMR.csh1_on ? 003u : 0u) | (cpu.CMR.csh2_on ? 014u : 0u);
csh2_on           777 src/dps8/dps8_cache.c   cpu.CMR.csh2_on = 0;
csh2_on           481 src/dps8/dps8_cpu.h     word1    csh2_on; // 1: The upper half of the cache memory is active and
csh2_on          7612 src/dps8/dps8_ins.c                   uint csh2_on    = getbits36_1 (cpu.CY, 55 - 36);
csh2_on          7614 src/dps8/dps8_ins.c                                (cpu.CMR.csh2_on == 0 && csh2_on != 0);
csh2_on          7616 src/dps8/dps8_ins.c                   cpu.CMR.csh2_on = (word1) csh2_on;
csh2_on          7915 src/dps8/dps8_ins.c                     putbits36_1 (& cpu.Ypair[1], 55 - 36, cpu.CMR.csh2_on);