cpu_dev 331 src/dps8/doAppendCycleAPUDataRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 289 src/dps8/doAppendCycleAPUDataRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 293 src/dps8/doAppendCycleAPUDataStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 406 src/dps8/doAppendCycleIndirectWordFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 592 src/dps8/doAppendCycleInstructionFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 332 src/dps8/doAppendCycleOperandRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 706 src/dps8/doAppendCycleOperandRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 292 src/dps8/doAppendCycleOperandStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 328 src/dps8/doAppendCycleRTCDOperandFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 77 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 103 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 195 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 239 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 259 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 283 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 316 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, "do_ITS_ITP sets XSF to 1\r\n"); cpu_dev 326 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 335 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 375 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 378 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 414 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 437 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 471 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: Cr=%06o\r\n", Cr); cpu_dev 475 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 505 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: TPR.CA=%06o\r\n", cpu_dev 514 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "RI_MOD: Td=%o\r\n", Td); cpu_dev 527 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 552 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 611 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 629 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 639 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 668 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 673 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 683 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 733 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 740 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 743 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 792 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 831 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 846 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 858 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 954 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 990 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1017 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1031 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1038 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1059 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1075 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1078 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1108 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1138 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1145 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1148 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1176 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1197 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1213 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1216 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1234 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1266 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1281 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1305 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1348 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1366 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1388 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1411 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1460 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1478 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1499 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1525 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 53 src/dps8/dps8_append.c # define DBGAPP(...) sim_debug (DBG_APPENDING, & cpu_dev, __VA_ARGS__) cpu_dev 1907 src/dps8/dps8_append.c sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n"); cpu_dev 748 src/dps8/dps8_cpu.c sim_msg ("Number of CPUs in system is %d\r\n", cpu_dev.numunits); cpu_dev 760 src/dps8/dps8_cpu.c cpu_dev.numunits = (uint32) n; cpu_dev 942 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to %s\r\n", cpu_dev 2142 src/dps8/dps8_cpu.c sim_debug (DBG_INFO, & cpu_dev, "CPU reset: Running\r\n"); cpu_dev 2215 src/dps8/dps8_cpu.c DEVICE cpu_dev = cpu_dev 2485 src/dps8/dps8_cpu.c cpu_dev 2518 src/dps8/dps8_cpu.c cpu_dev 2784 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "set_temporary_absolute_mode bit 29 sets XSF to 0\r\n"); cpu_dev 3102 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Cycle is %s\r\n", cpu_dev 3147 src/dps8/dps8_cpu.c sim_debug (DBG_INTR, & cpu_dev, "intr_pair_addr %u flag %d\r\n", cpu_dev 3150 src/dps8/dps8_cpu.c if_sim_debug (DBG_INTR, & cpu_dev) cpu_dev 3391 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, cpu_dev 3501 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fetchCycle bit 29 sets XSF to 0\r\n"); cpu_dev 3765 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3773 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4570 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 4596 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 4666 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 4749 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 4770 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 4779 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 4807 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 4816 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 4843 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 4859 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 4893 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012llo (%s)\r\n", addr - 1, cpu_dev 4917 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012"PRIo64" (%s)\r\n", addr, odd, ctx); cpu_dev 5057 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting absolute mode.\r\n"); cpu_dev 5066 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Keeping append mode.\r\n"); cpu_dev 5068 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting append mode.\r\n"); cpu_dev 5074 src/dps8/dps8_cpu.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 480 src/dps8/dps8_cpu.h extern DEVICE cpu_dev; cpu_dev 428 src/dps8/dps8_decimal.c cpu_dev 430 src/dps8/dps8_decimal.c cpu_dev 458 src/dps8/dps8_decimal.c cpu_dev 473 src/dps8/dps8_decimal.c cpu_dev 477 src/dps8/dps8_decimal.c cpu_dev 486 src/dps8/dps8_decimal.c cpu_dev 492 src/dps8/dps8_decimal.c cpu_dev 512 src/dps8/dps8_decimal.c cpu_dev 541 src/dps8/dps8_decimal.c cpu_dev 558 src/dps8/dps8_decimal.c cpu_dev 580 src/dps8/dps8_decimal.c cpu_dev 592 src/dps8/dps8_decimal.c cpu_dev 610 src/dps8/dps8_decimal.c cpu_dev 614 src/dps8/dps8_decimal.c cpu_dev 621 src/dps8/dps8_decimal.c cpu_dev 630 src/dps8/dps8_decimal.c cpu_dev 655 src/dps8/dps8_decimal.c cpu_dev 679 src/dps8/dps8_decimal.c cpu_dev 697 src/dps8/dps8_decimal.c cpu_dev 705 src/dps8/dps8_decimal.c cpu_dev 29 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 39 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 556 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteCache addr %06o\r\n", p->cachedAddr); cpu_dev 566 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 571 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 594 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 599 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 620 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadCache addr %06o\r\n", address); cpu_dev 644 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 647 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 665 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 667 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 670 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 688 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\r\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 691 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\r\n", p->address, n); cpu_dev 727 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx addr %06o n %u\r\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 731 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx %ld addr %06o n %u\r\n", eisaddr_idx, p->address, n); cpu_dev 757 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\r\n", cpu.du.Dk_PTR_W[eisaddr_idx]); cpu_dev 759 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\r\n", p->address); cpu_dev 770 src/dps8/dps8_eis.c cpu_dev 772 src/dps8/dps8_eis.c cpu_dev 792 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\r\n", __func__, addressN); cpu_dev 808 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 812 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 816 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 832 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 835 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 854 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\r\n", __func__, addressN); cpu_dev 870 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 874 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 878 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 894 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 897 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 959 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o\r\n", k, cpu.du.TAk[k - 1], residue, c); cpu_dev 961 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o\r\n", k, e -> TA [k - 1], residue, c); cpu_dev 1274 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\r\n", n, k - 1); cpu_dev 1279 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARb %u\r\n", k - 1); cpu_dev 1306 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARa %u\r\n", k - 1); cpu_dev 1428 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\r\n", n, k - 1); cpu_dev 1435 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "initial CN%u %u\r\n", k, CN); cpu_dev 1470 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %o\r\n", k, e->N[k-1]); cpu_dev 1516 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA4\r\n", cpu_dev 1552 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA6\r\n", cpu_dev 1566 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1579 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA9\r\n", cpu_dev 1738 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(cpup, ): N%u %0o\r\n", k, e->N[k-1]); cpu_dev 1841 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1845 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1884 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d AR%d\r\n", k, n); cpu_dev 1908 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\r\n", k, reg, (word36)e->N[k-1]); cpu_dev 1915 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d opdesc %012"PRIo64"\r\n", k, opDesc); cpu_dev 1916 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %u\r\n", k, e->N[k-1]); cpu_dev 2219 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2226 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2232 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2240 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2261 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o addend 0%o sum 0%o\r\n", augend, addend, sum); cpu_dev 2375 src/dps8/dps8_eis.c cpu_dev 2407 src/dps8/dps8_eis.c cpu_dev 2458 src/dps8/dps8_eis.c cpu_dev 2498 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2505 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2514 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2521 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2581 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2588 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2597 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2603 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2626 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd r 0%o\r\n", r); cpu_dev 2628 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\r\n", ARn, address, reg, r); cpu_dev 2914 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d r 0%"PRIo64"\r\n", sz, rcnt); cpu_dev 2930 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\r\n", sz, ARn, address, reg, r); cpu_dev 3007 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd augend 0%o addend 0%o sum 0%o\r\n", augend, addend, sum); cpu_dev 3187 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpc tally %d c1 %03o c2 %03o\r\n", cpu.du.CHTALLY, c1, c2); cpu_dev 4081 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4084 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4148 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4176 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4277 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4280 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4344 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4373 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4602 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4606 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4643 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #3\r\n"); cpu_dev 4683 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #4\r\n"); cpu_dev 4723 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #1\r\n"); cpu_dev 4754 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #2\r\n"); cpu_dev 5023 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #1\r\n"); cpu_dev 5055 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #2\r\n"); cpu_dev 5221 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "src: %d: %o\r\n", n, c); cpu_dev 5345 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 5347 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "inBuffer:"); cpu_dev 5349 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, " %02o", * q); cpu_dev 5350 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "\r\n"); cpu_dev 6030 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "LTE IT[%d]<=%d\r\n", e -> mopIF - 1, next); cpu_dev 6081 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC IF %d, srcTally %d, dstTally %d\r\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 6084 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC n %d, srcTally %d, dstTally %d\r\n", n, e->srcTally, e->dstTally); cpu_dev 6096 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC c %d (0%o)\r\n", c, c); cpu_dev 6099 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES off\r\n"); cpu_dev 6101 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is zero\r\n"); cpu_dev 6108 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is not zero\r\n"); cpu_dev 6122 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES on\r\n"); cpu_dev 6192 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLS n %d c %o\r\n", n, c); cpu_dev 6198 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6211 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6235 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6252 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is ON, the character is moved to the receiving field.\r\n"); cpu_dev 6294 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MORS mopIF %d src %d dst %d\r\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 6336 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC mopIF %d\r\n", e->mopIF); cpu_dev 6340 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC n %d srcTally %d dstTally %d\r\n", n, e->srcTally, e->dstTally); cpu_dev 6348 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC write to output buffer %o\r\n", *e->in); cpu_dev 6357 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC done\r\n"); cpu_dev 6688 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MOP %s(%o) %o\r\n", m -> mopName, mop, e->mopIF); cpu_dev 6692 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "getMop(e->m == NULL || e->m->f == NULL): mop:%d IF:%d\r\n", mop, e->mopIF); cpu_dev 6740 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6746 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor EISgetMop forced break\r\n"); cpu_dev 6771 src/dps8/dps8_eis.c cpu_dev 6777 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6797 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mop faults %o src %d dst %d mop %d\r\n", cpu_dev 6815 src/dps8/dps8_eis.c cpu_dev 6833 src/dps8/dps8_eis.c cpu_dev 6854 src/dps8/dps8_eis.c sim_debug(DBG_TRACEEXT, & cpu_dev, "mve\r\n"); cpu_dev 7151 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7155 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7383 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7876 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7879 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7882 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7921 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n1 %d sc1 %d\r\n", n1, sc1); cpu_dev 7952 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n2 %d\r\n", n2); cpu_dev 7974 src/dps8/dps8_eis.c if_sim_debug (DBG_CAC, & cpu_dev) cpu_dev 7985 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "mvn res: '%s'\r\n", res); cpu_dev 8107 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is neg %o\r\n", decNumberIsNegative(op1)); cpu_dev 8108 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is zero %o\r\n", decNumberIsZero(op1)); cpu_dev 8109 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "R %o\r\n", R); cpu_dev 8110 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Trunc %o\r\n", Trunc); cpu_dev 8111 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "TRUNC %o\r\n", TST_I_TRUNC); cpu_dev 8112 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "OMASK %o\r\n", TST_I_OMASK); cpu_dev 8113 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "tstOVFfault %o\r\n", tstOVFfault (cpup)); cpu_dev 8114 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "T %o\r\n", T); cpu_dev 8115 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "EOvr %o\r\n", EOvr); cpu_dev 8116 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Ovr %o\r\n", Ovr); cpu_dev 8249 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8520 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8524 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8738 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8909 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8913 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 9115 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb N1 %d N2 %d\r\n", e -> N1, e -> N2); cpu_dev 9153 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(min(e->N1, e->N2)) i %d b1 %d b2 %d\r\n", i, b1, b2); cpu_dev 9174 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 < e->N2) i %d b1fill %d b2 %d\r\n", i, b1, b2); cpu_dev 9195 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 > e->N2) i %d b1 %d b2fill %d\r\n", i, b1, b2); cpu_dev 9791 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 9967 src/dps8/dps8_eis.c cpu_dev 9992 src/dps8/dps8_eis.c cpu_dev 10003 src/dps8/dps8_eis.c cpu_dev 10025 src/dps8/dps8_eis.c cpu_dev 10046 src/dps8/dps8_eis.c cpu_dev 10067 src/dps8/dps8_eis.c cpu_dev 10087 src/dps8/dps8_eis.c cpu_dev 10094 src/dps8/dps8_eis.c cpu_dev 13011 src/dps8/dps8_eis.c cpu_dev 13013 src/dps8/dps8_eis.c cpu_dev 13041 src/dps8/dps8_eis.c cpu_dev 13056 src/dps8/dps8_eis.c cpu_dev 13060 src/dps8/dps8_eis.c cpu_dev 13071 src/dps8/dps8_eis.c cpu_dev 13077 src/dps8/dps8_eis.c cpu_dev 13097 src/dps8/dps8_eis.c cpu_dev 13187 src/dps8/dps8_eis.c cpu_dev 13204 src/dps8/dps8_eis.c cpu_dev 13226 src/dps8/dps8_eis.c cpu_dev 13238 src/dps8/dps8_eis.c cpu_dev 13252 src/dps8/dps8_eis.c cpu_dev 13256 src/dps8/dps8_eis.c cpu_dev 13263 src/dps8/dps8_eis.c cpu_dev 13272 src/dps8/dps8_eis.c cpu_dev 13318 src/dps8/dps8_eis.c cpu_dev 13355 src/dps8/dps8_eis.c cpu_dev 13373 src/dps8/dps8_eis.c cpu_dev 13381 src/dps8/dps8_eis.c cpu_dev 13563 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: clz1 %d clz2 %d\r\n",clz1,clz2); cpu_dev 13569 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF2 %d NQ %d\r\n", cpu_dev 13592 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv2d anomalous results"); } // divide by zero has already been checked before cpu_dev 13646 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\r\n", cpu_dev 13658 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: addzero n2 %d %s exp %d\r\n",n2,res,op3->exponent); cpu_dev 14005 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: clz1 %d clz2 %d\r\n",clz1,clz2); cpu_dev 14012 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF3 %d NQ %d\r\n", cpu_dev 14035 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv3d anomalous results"); } // divide by zero has already been checked before cpu_dev 14089 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 14103 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: addzero n3 %d %s exp %d\r\n",n3,res,op3->exponent); cpu_dev 402 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 417 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 620 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\r\n", TST_I_MIF); cpu_dev 631 src/dps8/dps8_faults.c cpu_dev 786 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Changing fault number to Trouble fault\r\n"); cpu_dev 827 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\r\n"); cpu_dev 837 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 841 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 930 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\r\n", TST_I_MIF); cpu_dev 972 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\r\n"); cpu_dev 1023 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "setG7fault CPU %d fault %d (%o)\r\n", cpu_dev 1058 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "set_FFV_fault CPU f_fault_no %u\r\n", cpu_dev 79 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 100 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 120 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 137 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 169 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 181 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 199 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 211 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 239 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 251 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 269 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 282 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 311 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 323 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 341 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 353 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 381 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 393 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 411 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 423 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 453 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 465 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 483 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 495 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 523 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 535 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 553 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 565 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 598 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 600 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 614 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 616 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 636 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 638 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 650 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 652 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 656 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 659 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 693 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 695 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 709 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 711 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 731 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 733 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 745 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 747 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 751 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 753 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 785 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 787 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 801 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 803 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 823 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 825 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 837 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 839 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 871 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 873 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 887 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 889 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 909 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 911 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 923 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 925 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 950 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 952 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 964 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 966 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 995 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 997 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1011 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 1013 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1033 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 1035 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1047 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 1049 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1087 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1090 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1107 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1110 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1134 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1137 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1156 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1159 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1211 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1214 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1231 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1234 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1258 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1261 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1281 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1284 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1320 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar address=%08o writeData=%012"PRIo64"\r\n", address, data); cpu_dev 1333 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1351 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1361 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1392 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1405 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1423 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1433 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1464 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1479 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1497 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1507 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1546 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1557 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1579 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1593 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1630 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1639 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1658 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1669 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1701 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1717 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1739 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1753 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1788 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1791 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1809 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1812 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1836 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1839 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1856 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1859 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1919 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1922 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1940 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1943 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1967 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1970 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1987 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1990 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 125 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 180 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 204 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 207 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 226 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 239 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 265 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 329 src/dps8/dps8_ins.c sim_debug (DBG_TRACE, & cpu_dev, "%s %05o:%06o\r\n", cpu_dev 345 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 349 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 355 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 524 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 661 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\r\n", __func__, cpu.cu.XSF); cpu_dev 1255 src/dps8/dps8_ins.c if_sim_debug (flag, &cpu_dev) cpu_dev 1269 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o|%06o %s\r\n", cpu_dev 1274 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\r\n", cpu.PPR.IC, where); cpu_dev 1281 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o|%06o %s\r\n", cpu_dev 1287 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o %s\r\n", cpu_dev 1297 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1315 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1335 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1354 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1874 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1878 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1905 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; offset is %06o\r\n", offset); cpu_dev 1909 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\r\n", Xn, cpu.rX[Xn]); cpu_dev 1922 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\r\n", Xn, cpu.rX[Xn]); cpu_dev 1938 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "initialize EIS descriptors\r\n"); cpu_dev 2001 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, cpu_dev 2018 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, cpu_dev 2173 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 2186 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\r\n", Xn, cpu.rX[Xn]); cpu_dev 2203 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\r\n", Xn, cpu.rX[Xn]); cpu_dev 2216 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\r\n", Xn, cpu.rX[Xn]); cpu_dev 2268 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally %d\r\n", x); cpu_dev 2270 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally runout\r\n"); cpu_dev 2274 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not tally runout\r\n"); cpu_dev 2282 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is zero terminate\r\n"); cpu_dev 2287 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not zero terminate\r\n"); cpu_dev 2292 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is neg terminate\r\n"); cpu_dev 2297 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not neg terminate\r\n"); cpu_dev 2302 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is carry terminate\r\n"); cpu_dev 2307 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not carry terminate\r\n"); cpu_dev 2312 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is overflow terminate\r\n"); cpu_dev 2330 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not terminate\r\n"); cpu_dev 2367 src/dps8/dps8_ins.c if_sim_debug (DBG_REGDUMP, & cpu_dev) { cpu_dev 2369 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\r\n", cpu_dev 2372 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10Lg\r\n", cpu_dev 2375 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10g\r\n", cpu_dev 2378 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[0]=%06o X[1]=%06o X[2]=%06o X[3]=%06o\r\n", cpu_dev 2380 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[4]=%06o X[5]=%06o X[6]=%06o X[7]=%06o\r\n", cpu_dev 2383 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPR, &cpu_dev, "PR%d/%s: SNR=%05o RNR=%o WORDNO=%06o BITNO:%02o ARCHAR:%o ARBITNO:%02o\r\n", cpu_dev 2387 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\r\n", cpu_dev 2389 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPDSBR, &cpu_dev, "ADDR:%08o BND:%05o U:%o STACK:%04o\r\n", cpu_dev 3022 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 5395 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "\r\n"); cpu_dev 5396 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5399 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5410 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> quot 1 %"PRId64"\r\n", quotient); cpu_dev 5411 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> rem 1 %"PRId64"\r\n", remainder); cpu_dev 5427 src/dps8/dps8_ins.c cpu_dev 5429 src/dps8/dps8_ins.c cpu_dev 5437 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5439 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5444 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5452 src/dps8/dps8_ins.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 5464 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rA (rem) %012"PRIo64"\r\n", cpu.rA); cpu_dev 5465 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rQ (quot) %012"PRIo64"\r\n", cpu.rQ); cpu_dev 6126 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6608 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7266 src/dps8/dps8_ins.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 7285 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7293 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7753 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ldt TR %d (%o)\r\n", cpu_dev 7803 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\r\n", cpu.rRALR); cpu_dev 8968 src/dps8/dps8_ins.c sim_debug (DBG_MSG, & cpu_dev, "BCE DIS causes CPU halt\r\n"); cpu_dev 9027 src/dps8/dps8_ins.c cpu_dev 9033 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "entered DIS_cycle\r\n"); cpu_dev 9062 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees an interrupt\r\n"); cpu_dev 9082 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees a TRO\r\n"); cpu_dev 9088 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS refetches\r\n"); cpu_dev 10108 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\r\n", cpu.TPR.CA); cpu_dev 10140 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 10191 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU interrupt return\r\n"); cpu_dev 10270 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU FIF REFETCH return\r\n"); cpu_dev 10278 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi refetch return\r\n"); cpu_dev 10298 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\r\n"); cpu_dev 10313 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi/FIF REFETCH return\r\n"); cpu_dev 10324 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\r\n"); cpu_dev 10359 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU OFL/DIV refetch return\r\n"); cpu_dev 10364 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU sync fault return\r\n"); cpu_dev 10378 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MMEx sync fault return\r\n"); cpu_dev 10388 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU LUF RESTART return\r\n"); cpu_dev 10411 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU ACV RESTART return\r\n"); cpu_dev 1218 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fmp A %012"PRIo64" Q %012"PRIo64" E %03o\r\n", cpu.rA, cpu.rQ, cpu.rE); cpu_dev 2310 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e1 %d %03o m1 %012"PRIo64" %012"PRIo64"\r\n", cpu_dev 2326 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e2 %d %03o m2 %012"PRIo64" %012"PRIo64"\r\n", cpu_dev 1465 src/dps8/dps8_scu.c for (uint cpun = 0; cpun < cpu_dev.numunits; cpun ++) cpu_dev 28 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || ((1 << current_running_cpu_idx) & dbgCPUMask)) && \ cpu_dev 29 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || \ cpu_dev 31 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ cpu_dev 32 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (! sim_deb_bar) || (! TST_I_NBAR)) && \ cpu_dev 36 src/dps8/dps8_simh.h ((dptr != & cpu_dev) | (((dbits) & DBG_TRACE) ? (sim_deb_skip_cnt ++ >= sim_deb_skip_limit) : \ cpu_dev 1795 src/dps8/dps8_sys.c cpu_dev.numunits = 1; cpu_dev 2608 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2729 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2748 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 4800 src/dps8/dps8_sys.c if (uptr == &cpu_dev.units[0]) cpu_dev 5016 src/dps8/dps8_sys.c & cpu_dev, // dev[0] is special to the scp interface; it is the 'default device' cpu_dev 283 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 356 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b res %012"PRIo64" flags %06o ovf %o\r\n", res, * flags, * ovf); cpu_dev 722 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 730 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 776 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 784 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 800 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\r\n", cpu_dev 803 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\r\n", cpu_dev 882 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\r\n", cpu_dev 885 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\r\n", cpu_dev 1222 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\r\n", op1.h, op1.l); cpu_dev 1223 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\r\n", op2.h, op2.l); cpu_dev 1226 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\r\n", op1s.h, op1s.l); cpu_dev 1227 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\r\n", op2s.h, op2s.l); cpu_dev 1229 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\r\n", (uint64_t) (op1>>64), (uint64_t) op1); cpu_dev 1230 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\r\n", (uint64_t) (op2>>64), (uint64_t) op2); cpu_dev 1233 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\r\n", (uint64_t) (op1s>>64), (uint64_t) op1s); cpu_dev 1234 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\r\n", (uint64_t) (op2s>>64), (uint64_t) op2s);