cpt1U 2115 src/dps8/dps8_cpu.c CPT (cpt1U, 16); // LUF cpt1U 2472 src/dps8/dps8_cpu.c CPT (cpt1U, 0); // Interrupt cycle cpt1U 2493 src/dps8/dps8_cpu.c CPT (cpt1U, 1); // safe store complete cpt1U 2510 src/dps8/dps8_cpu.c CPT (cpt1U, 2); // interrupt pending cpt1U 2519 src/dps8/dps8_cpu.c CPT (cpt1U, 3); // interrupt identified cpt1U 2533 src/dps8/dps8_cpu.c CPT (cpt1U, 4); // interrupt pair fetched cpt1U 2542 src/dps8/dps8_cpu.c CPT (cpt1U, 5); // interrupt pair spurious cpt1U 2560 src/dps8/dps8_cpu.c CPT (cpt1U, 13); // fetch cycle cpt1U 2626 src/dps8/dps8_cpu.c CPT (cpt1U, 14); // sampling interrupts cpt1U 2693 src/dps8/dps8_cpu.c CPT (cpt1U, 15); // interrupt cpt1U 2742 src/dps8/dps8_cpu.c cpt1U 2780 src/dps8/dps8_cpu.c CPT (cpt1U, 20); // not XEC or RPx cpt1U 2796 src/dps8/dps8_cpu.c CPT (cpt1U, 21); // go to exec cycle cpt1U 2939 src/dps8/dps8_cpu.c CPT (cpt1U, 22); // exec cycle cpt1U 2966 src/dps8/dps8_cpu.c CPT (cpt1U, 23); // execution complete cpt1U 2981 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 2996 src/dps8/dps8_cpu.c CPT (cpt1U, 24); // transfer instruction cpt1U 3014 src/dps8/dps8_cpu.c CPT (cpt1U, 9); // nbar set cpt1U 3023 src/dps8/dps8_cpu.c CPT (cpt1U, 10); // temporary absolute mode cpt1U 3054 src/dps8/dps8_cpu.c CPT (cpt1U, 25); // DIS instruction cpt1U 3232 src/dps8/dps8_cpu.c CPT (cpt1U, 26); // RPx instruction cpt1U 3246 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3271 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3300 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 3344 src/dps8/dps8_cpu.c CPT (cpt1U, 28); // enter fetch cycle cpt1U 3352 src/dps8/dps8_cpu.c CPT (cpt1U, 29); // sync. fault return cpt1U 3366 src/dps8/dps8_cpu.c CPT (cpt1U, 30); // fault cycle cpt1U 3411 src/dps8/dps8_cpu.c CPT (cpt1U, 31); // safe store complete cpt1U 3451 src/dps8/dps8_cpu.c CPT (cpt1U, 33); // set fault exec cycle cpt1U 1903 src/dps8/dps8_cpu.h #define cpt1U 0 // Instruction processing tracking