cpt1U 2111 src/dps8/dps8_cpu.c CPT (cpt1U, 16); // LUF cpt1U 2468 src/dps8/dps8_cpu.c CPT (cpt1U, 0); // Interrupt cycle cpt1U 2489 src/dps8/dps8_cpu.c CPT (cpt1U, 1); // safe store complete cpt1U 2506 src/dps8/dps8_cpu.c CPT (cpt1U, 2); // interrupt pending cpt1U 2515 src/dps8/dps8_cpu.c CPT (cpt1U, 3); // interrupt identified cpt1U 2529 src/dps8/dps8_cpu.c CPT (cpt1U, 4); // interrupt pair fetched cpt1U 2538 src/dps8/dps8_cpu.c CPT (cpt1U, 5); // interrupt pair spurious cpt1U 2556 src/dps8/dps8_cpu.c CPT (cpt1U, 13); // fetch cycle cpt1U 2622 src/dps8/dps8_cpu.c CPT (cpt1U, 14); // sampling interrupts cpt1U 2689 src/dps8/dps8_cpu.c CPT (cpt1U, 15); // interrupt cpt1U 2738 src/dps8/dps8_cpu.c cpt1U 2776 src/dps8/dps8_cpu.c CPT (cpt1U, 20); // not XEC or RPx cpt1U 2792 src/dps8/dps8_cpu.c CPT (cpt1U, 21); // go to exec cycle cpt1U 2935 src/dps8/dps8_cpu.c CPT (cpt1U, 22); // exec cycle cpt1U 2962 src/dps8/dps8_cpu.c CPT (cpt1U, 23); // execution complete cpt1U 2977 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 2992 src/dps8/dps8_cpu.c CPT (cpt1U, 24); // transfer instruction cpt1U 3010 src/dps8/dps8_cpu.c CPT (cpt1U, 9); // nbar set cpt1U 3019 src/dps8/dps8_cpu.c CPT (cpt1U, 10); // temporary absolute mode cpt1U 3050 src/dps8/dps8_cpu.c CPT (cpt1U, 25); // DIS instruction cpt1U 3228 src/dps8/dps8_cpu.c CPT (cpt1U, 26); // RPx instruction cpt1U 3242 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3267 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3296 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 3340 src/dps8/dps8_cpu.c CPT (cpt1U, 28); // enter fetch cycle cpt1U 3348 src/dps8/dps8_cpu.c CPT (cpt1U, 29); // sync. fault return cpt1U 3362 src/dps8/dps8_cpu.c CPT (cpt1U, 30); // fault cycle cpt1U 3407 src/dps8/dps8_cpu.c CPT (cpt1U, 31); // safe store complete cpt1U 3447 src/dps8/dps8_cpu.c CPT (cpt1U, 33); // set fault exec cycle cpt1U 1903 src/dps8/dps8_cpu.h #define cpt1U 0 // Instruction processing tracking