cpu_dev 331 src/dps8/doAppendCycleAPUDataRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 287 src/dps8/doAppendCycleAPUDataRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 291 src/dps8/doAppendCycleAPUDataStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 402 src/dps8/doAppendCycleIndirectWordFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 581 src/dps8/doAppendCycleInstructionFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 329 src/dps8/doAppendCycleOperandRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 701 src/dps8/doAppendCycleOperandRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 289 src/dps8/doAppendCycleOperandStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 326 src/dps8/doAppendCycleRTCDOperandFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 77 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 103 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 195 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 239 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 259 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 283 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 315 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, "do_ITS_ITP sets XSF to 1\n"); cpu_dev 325 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 334 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 374 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 377 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 413 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 436 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 470 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: Cr=%06o\n", Cr); cpu_dev 474 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 504 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: TPR.CA=%06o\n", cpu_dev 513 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "RI_MOD: Td=%o\n", Td); cpu_dev 526 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 551 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 610 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 628 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 638 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 667 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 672 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 682 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 733 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 740 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 743 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 792 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 831 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 846 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 858 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 954 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 990 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1017 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1031 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1038 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1059 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1075 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1078 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1108 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1138 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1145 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1148 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1176 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1197 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1213 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1216 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1234 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1266 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1281 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1305 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1348 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1366 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1388 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1411 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1460 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1478 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1499 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1525 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 53 src/dps8/dps8_append.c # define DBGAPP(...) sim_debug (DBG_APPENDING, & cpu_dev, __VA_ARGS__) cpu_dev 1891 src/dps8/dps8_append.c sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 706 src/dps8/dps8_cpu.c sim_msg ("Number of CPUs in system is %d\n", cpu_dev.numunits); cpu_dev 718 src/dps8/dps8_cpu.c cpu_dev.numunits = (uint32) n; cpu_dev 900 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to %s\n", cpu_dev 1577 src/dps8/dps8_cpu.c sim_debug (DBG_INFO, & cpu_dev, "CPU reset: Running\n"); cpu_dev 1650 src/dps8/dps8_cpu.c DEVICE cpu_dev = cpu_dev 1873 src/dps8/dps8_cpu.c cpu_dev 1906 src/dps8/dps8_cpu.c cpu_dev 2117 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "set_temporary_absolute_mode bit 29 sets XSF to 0\n"); cpu_dev 2158 src/dps8/dps8_cpu.c set_cpu_idx (cpu_dev.numunits - 1); cpu_dev 2163 src/dps8/dps8_cpu.c for (c = 0; c < cpu_dev.numunits; c ++) cpu_dev 2169 src/dps8/dps8_cpu.c if (c == cpu_dev.numunits) cpu_dev 2174 src/dps8/dps8_cpu.c set_cpu_idx ((current + 1) % cpu_dev.numunits); cpu_dev 2335 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Cycle is %s\n", cpu_dev 2371 src/dps8/dps8_cpu.c sim_debug (DBG_INTR, & cpu_dev, "intr_pair_addr %u flag %d\n", cpu_dev 2374 src/dps8/dps8_cpu.c if_sim_debug (DBG_INTR, & cpu_dev) cpu_dev 2554 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, cpu_dev 2657 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fetchCycle bit 29 sets XSF to 0\n"); cpu_dev 2759 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 2767 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3513 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3541 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3608 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3690 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3708 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 3717 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3745 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3754 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3781 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3796 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 3830 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012llo (%s)\n", addr - 1, cpu_dev 3856 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012"PRIo64" (%s)\n", addr, odd, ctx); cpu_dev 3992 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting absolute mode.\n"); cpu_dev 4001 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Keeping append mode.\n"); cpu_dev 4003 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting append mode.\n"); cpu_dev 4009 src/dps8/dps8_cpu.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 469 src/dps8/dps8_cpu.h extern DEVICE cpu_dev; cpu_dev 428 src/dps8/dps8_decimal.c cpu_dev 430 src/dps8/dps8_decimal.c cpu_dev 458 src/dps8/dps8_decimal.c cpu_dev 473 src/dps8/dps8_decimal.c cpu_dev 477 src/dps8/dps8_decimal.c cpu_dev 486 src/dps8/dps8_decimal.c cpu_dev 492 src/dps8/dps8_decimal.c cpu_dev 512 src/dps8/dps8_decimal.c cpu_dev 541 src/dps8/dps8_decimal.c cpu_dev 558 src/dps8/dps8_decimal.c cpu_dev 580 src/dps8/dps8_decimal.c cpu_dev 592 src/dps8/dps8_decimal.c cpu_dev 610 src/dps8/dps8_decimal.c cpu_dev 614 src/dps8/dps8_decimal.c cpu_dev 621 src/dps8/dps8_decimal.c cpu_dev 630 src/dps8/dps8_decimal.c cpu_dev 655 src/dps8/dps8_decimal.c cpu_dev 679 src/dps8/dps8_decimal.c cpu_dev 697 src/dps8/dps8_decimal.c cpu_dev 705 src/dps8/dps8_decimal.c cpu_dev 29 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 39 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 556 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteCache addr %06o\n", p->cachedAddr); cpu_dev 566 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 571 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 594 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 599 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 620 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadCache addr %06o\n", address); cpu_dev 644 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 647 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 665 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 667 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 670 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 688 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 691 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", p->address, n); cpu_dev 727 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 731 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx %ld addr %06o n %u\n", eisaddr_idx, p->address, n); cpu_dev 757 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", cpu.du.Dk_PTR_W[eisaddr_idx]); cpu_dev 759 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", p->address); cpu_dev 770 src/dps8/dps8_eis.c cpu_dev 772 src/dps8/dps8_eis.c cpu_dev 792 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); cpu_dev 808 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 812 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 816 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 832 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 835 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 854 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); cpu_dev 870 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 874 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 878 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 894 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 897 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 959 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, cpu.du.TAk[k - 1], residue, c); cpu_dev 961 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, e -> TA [k - 1], residue, c); cpu_dev 1274 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); cpu_dev 1279 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARb %u\n", k - 1); cpu_dev 1306 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARa %u\n", k - 1); cpu_dev 1422 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); cpu_dev 1429 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "initial CN%u %u\n", k, CN); cpu_dev 1464 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %o\n", k, e->N[k-1]); cpu_dev 1508 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA4\n", cpu_dev 1532 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA6\n", cpu_dev 1546 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1558 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA9\n", cpu_dev 1713 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(cpup, ): N%u %0o\n", k, e->N[k-1]); cpu_dev 1813 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1817 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1856 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d AR%d\n", k, n); cpu_dev 1876 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]); cpu_dev 1883 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d opdesc %012"PRIo64"\n", k, opDesc); cpu_dev 1884 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %u\n", k, e->N[k-1]); cpu_dev 2109 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2116 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2122 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2130 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2151 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 2265 src/dps8/dps8_eis.c cpu_dev 2297 src/dps8/dps8_eis.c cpu_dev 2348 src/dps8/dps8_eis.c cpu_dev 2388 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2395 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2404 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2411 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2471 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2478 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2487 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2493 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2516 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd r 0%o\n", r); cpu_dev 2518 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); cpu_dev 2804 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d r 0%"PRIo64"\n", sz, rcnt); cpu_dev 2820 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); cpu_dev 2897 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 3076 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpc tally %d c1 %03o c2 %03o\n", cpu.du.CHTALLY, c1, c2); cpu_dev 3953 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3956 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4020 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4047 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4148 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4151 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4215 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4243 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4472 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4476 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4513 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #3\n"); cpu_dev 4553 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #4\n"); cpu_dev 4593 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #1\n"); cpu_dev 4623 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #2\n"); cpu_dev 4888 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #1\n"); cpu_dev 4919 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #2\n"); cpu_dev 5082 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "src: %d: %o\n", n, c); cpu_dev 5206 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 5208 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "inBuffer:"); cpu_dev 5210 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, " %02o", * q); cpu_dev 5211 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "\n"); cpu_dev 5883 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "LTE IT[%d]<=%d\n", e -> mopIF - 1, next); cpu_dev 5934 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC IF %d, srcTally %d, dstTally %d\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 5937 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC n %d, srcTally %d, dstTally %d\n", n, e->srcTally, e->dstTally); cpu_dev 5949 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC c %d (0%o)\n", c, c); cpu_dev 5952 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES off\n"); cpu_dev 5954 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is zero\n"); cpu_dev 5961 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is not zero\n"); cpu_dev 5975 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES on\n"); cpu_dev 6045 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLS n %d c %o\n", n, c); cpu_dev 6051 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6064 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6088 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6105 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is ON, the character is moved to the receiving field.\n"); cpu_dev 6147 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MORS mopIF %d src %d dst %d\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 6189 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC mopIF %d\n", e->mopIF); cpu_dev 6193 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC n %d srcTally %d dstTally %d\n", n, e->srcTally, e->dstTally); cpu_dev 6201 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC write to output buffer %o\n", *e->in); cpu_dev 6210 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC done\n"); cpu_dev 6541 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MOP %s(%o) %o\n", m -> mopName, mop, e->mopIF); cpu_dev 6545 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "getMop(e->m == NULL || e->m->f == NULL): mop:%d IF:%d\n", mop, e->mopIF); cpu_dev 6593 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6599 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor EISgetMop forced break\n"); cpu_dev 6624 src/dps8/dps8_eis.c cpu_dev 6630 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mop faults %o src %d dst %d mop %d\n", cpu_dev 6668 src/dps8/dps8_eis.c cpu_dev 6686 src/dps8/dps8_eis.c cpu_dev 6707 src/dps8/dps8_eis.c sim_debug(DBG_TRACEEXT, & cpu_dev, "mve\n"); cpu_dev 7004 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7008 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7233 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7712 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7715 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7718 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7757 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n1 %d sc1 %d\n", n1, sc1); cpu_dev 7788 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n2 %d\n", n2); cpu_dev 7810 src/dps8/dps8_eis.c if_sim_debug (DBG_CAC, & cpu_dev) cpu_dev 7821 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "mvn res: '%s'\n", res); cpu_dev 7943 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is neg %o\n", decNumberIsNegative(op1)); cpu_dev 7944 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is zero %o\n", decNumberIsZero(op1)); cpu_dev 7945 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "R %o\n", R); cpu_dev 7946 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Trunc %o\n", Trunc); cpu_dev 7947 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "TRUNC %o\n", TST_I_TRUNC); cpu_dev 7948 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "OMASK %o\n", TST_I_OMASK); cpu_dev 7949 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "tstOVFfault %o\n", tstOVFfault (cpup)); cpu_dev 7950 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "T %o\n", T); cpu_dev 7951 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "EOvr %o\n", EOvr); cpu_dev 7952 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Ovr %o\n", Ovr); cpu_dev 8085 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8354 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8358 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8570 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8739 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8743 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8943 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb N1 %d N2 %d\n", e -> N1, e -> N2); cpu_dev 8970 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(min(e->N1, e->N2)) i %d b1 %d b2 %d\n", i, b1, b2); cpu_dev 8990 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 < e->N2) i %d b1fill %d b2 %d\n", i, b1, b2); cpu_dev 9010 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 > e->N2) i %d b1 %d b2fill %d\n", i, b1, b2); cpu_dev 9606 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 9782 src/dps8/dps8_eis.c cpu_dev 9807 src/dps8/dps8_eis.c cpu_dev 9818 src/dps8/dps8_eis.c cpu_dev 9840 src/dps8/dps8_eis.c cpu_dev 9861 src/dps8/dps8_eis.c cpu_dev 9882 src/dps8/dps8_eis.c cpu_dev 9902 src/dps8/dps8_eis.c cpu_dev 9909 src/dps8/dps8_eis.c cpu_dev 12491 src/dps8/dps8_eis.c cpu_dev 12493 src/dps8/dps8_eis.c cpu_dev 12521 src/dps8/dps8_eis.c cpu_dev 12536 src/dps8/dps8_eis.c cpu_dev 12540 src/dps8/dps8_eis.c cpu_dev 12551 src/dps8/dps8_eis.c cpu_dev 12557 src/dps8/dps8_eis.c cpu_dev 12577 src/dps8/dps8_eis.c cpu_dev 12667 src/dps8/dps8_eis.c cpu_dev 12684 src/dps8/dps8_eis.c cpu_dev 12706 src/dps8/dps8_eis.c cpu_dev 12718 src/dps8/dps8_eis.c cpu_dev 12732 src/dps8/dps8_eis.c cpu_dev 12736 src/dps8/dps8_eis.c cpu_dev 12743 src/dps8/dps8_eis.c cpu_dev 12752 src/dps8/dps8_eis.c cpu_dev 12798 src/dps8/dps8_eis.c cpu_dev 12835 src/dps8/dps8_eis.c cpu_dev 12853 src/dps8/dps8_eis.c cpu_dev 12861 src/dps8/dps8_eis.c cpu_dev 13043 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: clz1 %d clz2 %d\n",clz1,clz2); cpu_dev 13049 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF2 %d NQ %d\n", cpu_dev 13072 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv2d anomalous results"); } // divide by zero has already been checked before cpu_dev 13126 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n", cpu_dev 13138 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: addzero n2 %d %s exp %d\n",n2,res,op3->exponent); cpu_dev 13485 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: clz1 %d clz2 %d\n",clz1,clz2); cpu_dev 13492 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF3 %d NQ %d\n", cpu_dev 13515 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv3d anomalous results"); } // divide by zero has already been checked before cpu_dev 13569 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 13583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: addzero n3 %d %s exp %d\n",n3,res,op3->exponent); cpu_dev 394 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 408 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 545 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); cpu_dev 547 src/dps8/dps8_faults.c cpu_dev 673 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Changing fault number to Trouble fault\n"); cpu_dev 716 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n"); cpu_dev 726 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 730 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 805 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); cpu_dev 849 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n"); cpu_dev 900 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "setG7fault CPU %d fault %d (%o) sub %"PRId64" %"PRIo64"\n", cpu_dev 912 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "set_FFV_fault CPU f_fault_no %u\n", cpu_dev 79 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 100 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 120 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 137 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 169 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 181 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 199 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 211 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 239 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 251 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 269 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 282 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 311 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 323 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 341 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 353 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 381 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 393 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 411 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 423 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 453 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 465 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 483 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 495 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 523 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 535 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 553 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 565 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 598 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 600 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 614 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 616 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 636 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 638 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 650 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 652 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 656 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 659 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 693 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 695 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 709 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 711 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 731 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 733 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 745 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 747 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 751 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 753 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 785 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 787 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 801 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 803 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 823 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 825 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 837 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 839 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 871 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 873 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 887 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 889 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 909 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 911 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 923 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 925 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 950 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 952 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 964 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 966 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 995 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 997 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1011 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 1013 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1033 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 1035 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1047 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 1049 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1087 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1090 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1107 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1110 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1134 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1137 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1156 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1159 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1211 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1214 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1231 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1234 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1258 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1261 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1281 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1284 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1320 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar address=%08o writeData=%012"PRIo64"\n", address, data); cpu_dev 1333 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1351 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1361 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1391 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1403 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1421 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1431 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1462 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1477 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1495 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1505 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1544 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1555 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1577 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1591 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1627 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1635 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1654 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1665 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1696 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1711 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1733 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1747 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1781 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1784 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1801 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1804 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1828 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1831 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1848 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1851 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1910 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1913 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1930 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1933 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1957 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1960 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1977 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1980 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 124 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 179 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 203 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 206 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 225 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 238 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 264 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 322 src/dps8/dps8_ins.c sim_debug (DBG_TRACE, & cpu_dev, "%s %05o:%06o\n", cpu_dev 338 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 342 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 348 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 503 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 640 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\n", __func__, cpu.cu.XSF); cpu_dev 1217 src/dps8/dps8_ins.c if_sim_debug (flag, &cpu_dev) cpu_dev 1231 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o|%06o %s\n", cpu_dev 1236 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); cpu_dev 1243 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o|%06o %s\n", cpu_dev 1249 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o %s\n", cpu_dev 1259 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1277 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1297 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1316 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1835 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1839 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1866 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; offset is %06o\n", offset); cpu_dev 1870 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]); cpu_dev 1877 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 1893 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "initialize EIS descriptors\n"); cpu_dev 1951 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, cpu_dev 1968 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, cpu_dev 2115 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 2127 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2143 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2155 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2207 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally %d\n", x); cpu_dev 2209 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally runout\n"); cpu_dev 2213 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not tally runout\n"); cpu_dev 2221 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is zero terminate\n"); cpu_dev 2226 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not zero terminate\n"); cpu_dev 2231 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is neg terminate\n"); cpu_dev 2236 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not neg terminate\n"); cpu_dev 2241 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is carry terminate\n"); cpu_dev 2246 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not carry terminate\n"); cpu_dev 2251 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is overflow terminate\n"); cpu_dev 2264 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not terminate\n"); cpu_dev 2300 src/dps8/dps8_ins.c if_sim_debug (DBG_REGDUMP, & cpu_dev) { cpu_dev 2302 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\n", cpu_dev 2305 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10Lg\n", cpu_dev 2308 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10g\n", cpu_dev 2311 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[0]=%06o X[1]=%06o X[2]=%06o X[3]=%06o\n", cpu_dev 2313 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[4]=%06o X[5]=%06o X[6]=%06o X[7]=%06o\n", cpu_dev 2316 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPR, &cpu_dev, "PR%d/%s: SNR=%05o RNR=%o WORDNO=%06o BITNO:%02o ARCHAR:%o ARBITNO:%02o\n", cpu_dev 2320 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\n", cpu_dev 2322 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPDSBR, &cpu_dev, "ADDR:%08o BND:%05o U:%o STACK:%04o\n", cpu_dev 2944 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 5245 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "\n"); cpu_dev 5246 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5249 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5260 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> quot 1 %"PRId64"\n", quotient); cpu_dev 5261 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> rem 1 %"PRId64"\n", remainder); cpu_dev 5277 src/dps8/dps8_ins.c cpu_dev 5279 src/dps8/dps8_ins.c cpu_dev 5287 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5289 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5294 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 5302 src/dps8/dps8_ins.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 5314 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rA (rem) %012"PRIo64"\n", cpu.rA); cpu_dev 5315 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rQ (quot) %012"PRIo64"\n", cpu.rQ); cpu_dev 5976 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6458 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7113 src/dps8/dps8_ins.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 7132 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7140 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7564 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ldt TR %d (%o)\n", cpu_dev 7614 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\n", cpu.rRALR); cpu_dev 8705 src/dps8/dps8_ins.c sim_debug (DBG_MSG, & cpu_dev, "BCE DIS causes CPU halt\n"); cpu_dev 8725 src/dps8/dps8_ins.c cpu_dev 8735 src/dps8/dps8_ins.c sim_debug (DBG_MSG, & cpu_dev, "sys_trouble$die DIS causes CPU halt\n"); cpu_dev 8740 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "entered DIS_cycle\n"); cpu_dev 8767 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees an interrupt\n"); cpu_dev 8784 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees a TRO\n"); cpu_dev 8790 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS refetches\n"); cpu_dev 9736 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA); cpu_dev 9768 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 9792 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU interrupt return\n"); cpu_dev 9871 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU FIF REFETCH return\n"); cpu_dev 9879 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi refetch return\n"); cpu_dev 9899 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n"); cpu_dev 9914 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi/FIF REFETCH return\n"); cpu_dev 9925 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n"); cpu_dev 9956 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU sync fault return\n"); cpu_dev 9970 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MMEx sync fault return\n"); cpu_dev 9980 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU LUF RESTART return\n"); cpu_dev 9997 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU ACV RESTART return\n"); cpu_dev 1218 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fmp A %012"PRIo64" Q %012"PRIo64" E %03o\n", cpu.rA, cpu.rQ, cpu.rE); cpu_dev 2310 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e1 %d %03o m1 %012"PRIo64" %012"PRIo64"\n", cpu_dev 2326 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e2 %d %03o m2 %012"PRIo64" %012"PRIo64"\n", cpu_dev 1350 src/dps8/dps8_scu.c for (uint cpun = 0; cpun < cpu_dev.numunits; cpun ++) cpu_dev 28 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || ((1 << current_running_cpu_idx) & dbgCPUMask)) && \ cpu_dev 29 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || \ cpu_dev 31 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ cpu_dev 32 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (! sim_deb_bar) || (! TST_I_NBAR)) && \ cpu_dev 36 src/dps8/dps8_simh.h ((dptr != & cpu_dev) | (((dbits) & DBG_TRACE) ? (sim_deb_skip_cnt ++ >= sim_deb_skip_limit) : \ cpu_dev 1770 src/dps8/dps8_sys.c cpu_dev.numunits = 1; cpu_dev 2563 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2684 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2703 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 4743 src/dps8/dps8_sys.c if (uptr == &cpu_dev.units[0]) cpu_dev 4947 src/dps8/dps8_sys.c & cpu_dev, // dev[0] is special to the scp interface; it is the 'default device' cpu_dev 175 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 248 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b res %012"PRIo64" flags %06o ovf %o\n", res, * flags, * ovf); cpu_dev 614 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 622 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 668 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 676 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 692 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", cpu_dev 695 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", cpu_dev 774 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", cpu_dev 777 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", cpu_dev 1114 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", op1.h, op1.l); cpu_dev 1115 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", op2.h, op2.l); cpu_dev 1118 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", op1s.h, op1s.l); cpu_dev 1119 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", op2s.h, op2s.l); cpu_dev 1121 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1>>64), (uint64_t) op1); cpu_dev 1122 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2>>64), (uint64_t) op2); cpu_dev 1125 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1s>>64), (uint64_t) op1s); cpu_dev 1126 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2s>>64), (uint64_t) op2s);