cpt1U 2060 src/dps8/dps8_cpu.c CPT (cpt1U, 16); // LUF cpt1U 2342 src/dps8/dps8_cpu.c CPT (cpt1U, 0); // Interrupt cycle cpt1U 2363 src/dps8/dps8_cpu.c CPT (cpt1U, 1); // safe store complete cpt1U 2380 src/dps8/dps8_cpu.c CPT (cpt1U, 2); // interrupt pending cpt1U 2389 src/dps8/dps8_cpu.c CPT (cpt1U, 3); // interrupt identified cpt1U 2403 src/dps8/dps8_cpu.c CPT (cpt1U, 4); // interrupt pair fetched cpt1U 2412 src/dps8/dps8_cpu.c CPT (cpt1U, 5); // interrupt pair spurious cpt1U 2430 src/dps8/dps8_cpu.c CPT (cpt1U, 13); // fetch cycle cpt1U 2496 src/dps8/dps8_cpu.c CPT (cpt1U, 14); // sampling interrupts cpt1U 2563 src/dps8/dps8_cpu.c CPT (cpt1U, 15); // interrupt cpt1U 2612 src/dps8/dps8_cpu.c cpt1U 2650 src/dps8/dps8_cpu.c CPT (cpt1U, 20); // not XEC or RPx cpt1U 2666 src/dps8/dps8_cpu.c CPT (cpt1U, 21); // go to exec cycle cpt1U 2675 src/dps8/dps8_cpu.c CPT (cpt1U, 22); // exec cycle cpt1U 2704 src/dps8/dps8_cpu.c CPT (cpt1U, 23); // execution complete cpt1U 2719 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 2734 src/dps8/dps8_cpu.c CPT (cpt1U, 24); // transfer instruction cpt1U 2752 src/dps8/dps8_cpu.c CPT (cpt1U, 9); // nbar set cpt1U 2761 src/dps8/dps8_cpu.c CPT (cpt1U, 10); // temporary absolute mode cpt1U 2792 src/dps8/dps8_cpu.c CPT (cpt1U, 25); // DIS instruction cpt1U 2961 src/dps8/dps8_cpu.c CPT (cpt1U, 26); // RPx instruction cpt1U 2975 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3000 src/dps8/dps8_cpu.c CPT (cpt1U, 12); // cu restored cpt1U 3029 src/dps8/dps8_cpu.c CPT (cpt1U, 27); // XEx instruction cpt1U 3073 src/dps8/dps8_cpu.c CPT (cpt1U, 28); // enter fetch cycle cpt1U 3081 src/dps8/dps8_cpu.c CPT (cpt1U, 29); // sync. fault return cpt1U 3095 src/dps8/dps8_cpu.c CPT (cpt1U, 30); // fault cycle cpt1U 3140 src/dps8/dps8_cpu.c CPT (cpt1U, 31); // safe store complete cpt1U 3180 src/dps8/dps8_cpu.c CPT (cpt1U, 33); // set fault exec cycle cpt1U 1875 src/dps8/dps8_cpu.h #define cpt1U 0 // Instruction processing tracking