cachedR1          143 src/dps8/doAppendCycleInstructionFetch.h   word3 cachedR1;
cachedR1          148 src/dps8/doAppendCycleInstructionFetch.h       ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
cachedR1          536 src/dps8/doAppendCycleInstructionFetch.h     if (cachedR1 != RSDWH_R1) {
cachedR1          537 src/dps8/doAppendCycleInstructionFetch.h       sim_printf ("cachedR1 %01o != RSDWH_R1 %01o\r\n", cachedR1, RSDWH_R1);
cachedR1          130 src/dps8/doAppendCycleOperandRead.h   word3 cachedR1;
cachedR1          135 src/dps8/doAppendCycleOperandRead.h       ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
cachedR1          139 src/dps8/doAppendCycleOperandRead.h             cachedP, cachedAddress, cachedR1, cachedPaged);
cachedR1          653 src/dps8/doAppendCycleOperandRead.h     if (cachedR1 != RSDWH_R1) {
cachedR1          655 src/dps8/doAppendCycleOperandRead.h               cachedR1, RSDWH_R1);