TRR 27 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 140 src/dps8/doAppendCycleABSA.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 151 src/dps8/doAppendCycleABSA.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 282 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 25 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 152 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 163 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 185 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 188 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 189 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("ACV5 TRR %o R1 %o\r\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 198 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 348 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 25 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 149 src/dps8/doAppendCycleAPUDataRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 160 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 301 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 25 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 152 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 155 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 156 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("ACV5 TRR %o R1 %o\r\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 165 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 304 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 61 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 247 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 258 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 441 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); TRR 445 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 446 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(O) Set TRR to %o\r\n", cpu.TPR.TRR); TRR 456 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); TRR 460 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 461 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(P) Set TRR to %o\r\n", cpu.TPR.TRR); TRR 475 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 77 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 320 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TRR 322 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(C) ACV1 ! ( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\r\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 337 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR > cpu.PPR.PRR) TRR 338 src/dps8/doAppendCycleInstructionFetch.h sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\r\n", cpu.TPR.TRR, cpu.PPR.PRR); TRR 340 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.PPR.PRR) { TRR 385 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TRR 387 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\r\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 402 src/dps8/doAppendCycleInstructionFetch.h if (cpu.PPR.PRR != cpu.TPR.TRR) { TRR 626 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[7].RNR = cpu.TPR.TRR; TRR 654 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR == 0) { TRR 671 src/dps8/doAppendCycleInstructionFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 25 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 154 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 165 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 187 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 190 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 191 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("ACV5 TRR %o R1 %o\r\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 200 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 355 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 67 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 319 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 330 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 390 src/dps8/doAppendCycleOperandRead.h cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); TRR 426 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R3) { TRR 436 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1) { TRR 446 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.PPR.PRR) { TRR 458 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o SDW->R2 %o\r\n", cpu.TPR.TRR, cpu.SDW->R2); TRR 461 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 463 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.SDW->R2; TRR 466 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o\r\n", cpu.TPR.TRR); TRR 486 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TRR 488 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\r\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 503 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR != cpu.TPR.TRR) { TRR 768 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == 0) { TRR 782 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == cpu.PPR.PRR) { TRR 788 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; TRR 789 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(N) STACK %05o TRR %o\r\n", cpu.DSBR.STACK, cpu.TPR.TRR); TRR 794 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].RNR = cpu.TPR.TRR; TRR 803 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PRR = cpu.TPR.TRR; TRR 819 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 25 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 147 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 150 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 151 src/dps8/doAppendCycleOperandStore.h DBGAPP ("ACV5 TRR %o R1 %o\r\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 160 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 309 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 25 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 86 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\r\n", cpu.TPR.TSR, cpu.TPR.TRR); TRR 178 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 189 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 352 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 376 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR == 0) { TRR 394 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 222 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.RSDWH_R1, cpu.TPR.TRR); TRR 261 src/dps8/dps8_addrmods.c GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR, TRR 262 src/dps8/dps8_addrmods.c max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR)); TRR 264 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR); TRR 1220 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR); TRR 1290 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.TRR); TRR 1442 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) TRR 1455 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1489 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1492 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R1) TRR 1495 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R1); TRR 1505 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1534 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || TRR 1535 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) TRR 1539 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 1555 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) TRR 1557 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); TRR 1559 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.PPR.PRR) TRR 1610 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); TRR 1648 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R3) TRR 1659 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1) TRR 1670 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) TRR 1686 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R2); TRR 1689 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) TRR 1692 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.SDW->R2; TRR 1695 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(E1): CALL6 TPR.TRR %o\r\n", cpu.TPR.TRR); TRR 1715 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || TRR 1716 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) TRR 1720 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 1736 src/dps8/dps8_append.c if (cpu.PPR.PRR != cpu.TPR.TRR) TRR 2045 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 2108 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; TRR 2136 src/dps8/dps8_append.c if (cpu.TPR.TRR == 0) TRR 2153 src/dps8/dps8_append.c if (cpu.TPR.TRR == cpu.PPR.PRR) TRR 2162 src/dps8/dps8_append.c cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; TRR 2164 src/dps8/dps8_append.c cpu.DSBR.STACK, cpu.TPR.TRR); TRR 2169 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; TRR 2178 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR; TRR 2196 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); TRR 2200 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 2201 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(O) Set TRR to %o\r\n", cpu.TPR.TRR); TRR 2211 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); TRR 2215 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 2216 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(P) Set TRR to %o\r\n", cpu.TPR.TRR); TRR 2230 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 2927 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; TRR 3065 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 3267 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 3286 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 3498 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 3806 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 3950 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; TRR 5283 src/dps8/dps8_cpu.c putbits36_3 (& w1, 24, cpu.TPR.TRR); TRR 83 src/dps8/dps8_cpu.h word3 TRR; // The current effective ring number TRR 557 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 563 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 589 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 615 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 621 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 640 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 644 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 659 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 665 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\r\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 680 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 799 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 803 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 826 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 840 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 861 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 865 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 888 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 902 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 1270 src/dps8/dps8_eis.c cpu.TPR.TRR, TRR 1419 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 1639 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 1691 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 1881 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 118 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 197 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 267 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 339 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 409 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 481 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 551 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 634 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 729 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 821 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 907 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 948 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1031 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1131 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1255 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1349 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1421 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1495 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1577 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1656 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1736 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1833 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1964 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 430 src/dps8/dps8_ins.c putbits36_3 (& words[2], 0, cpu.TPR.TRR); TRR 714 src/dps8/dps8_ins.c cpu.TPR.TRR = getbits36_3 (words[2], 0); TRR 1182 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; TRR 1960 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 2014 src/dps8/dps8_ins.c cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR); TRR 2016 src/dps8/dps8_ins.c cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 2020 src/dps8/dps8_ins.c n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); TRR 2038 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; TRR 2128 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 2789 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TRR 2967 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TRR 3101 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TRR 3539 src/dps8/dps8_ins.c cpu.rA = cpu.TPR.TRR & MASK3; TRR 7060 src/dps8/dps8_ins.c cpu.PR[n].RNR = max3 (Crr, cpu.SDW->R1, cpu.TPR.TRR); TRR 28 src/dps8/dps8_mp.h word3 TRR; TRR 4136 src/dps8/dps8_sys.c { "cpus[].TPR.TRR", SYM_STRUCT_OFFSET, SYM_UINT8_3, offsetof (struct tpr_s, TRR) }, TRR 426 src/dps8/panelScraper.c SETL (bank_a, 0+3, cpu.TPR.TRR, 3); TRR 811 src/dps8/panelScraper.c