Xn 1864 src/dps8/dps8_ins.c uint Xn = X (Td); // Get Xn of next instruction Xn 1865 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]); Xn 1867 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK; Xn 1868 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 1870 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpt 1st"); Xn 1872 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2116 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); Xn 2117 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; Xn 2118 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 2120 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpt delta"); Xn 2122 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2132 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); Xn 2133 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; Xn 2134 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 2136 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpd delta even"); Xn 2138 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2144 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IRODD, 36 - 3); Xn 2145 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; Xn 2146 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; Xn 2148 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rpd delta odd"); Xn 2150 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); Xn 2273 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); Xn 2276 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.lnk; Xn 2278 src/dps8/dps8_ins.c HDBGRegXW (Xn, "rl");