TA2 582 src/dps8/dps8_cpu.h # define TA2 cpu.du.TAk[1] TA2 588 src/dps8/dps8_cpu.h # define TA2 TA [1] TA2 4366 src/dps8/dps8_eis.c switch (TA2) TA2 4368 src/dps8/dps8_eis.c switch (e -> TA2) TA2 4425 src/dps8/dps8_eis.c (TA2 == 2); // (6-4 move) TA2 4428 src/dps8/dps8_eis.c (e -> TA2 == 2); // (6-4 move) TA2 4436 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, TA1, TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); TA2 4438 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, e -> TA1, e -> TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); TA2 4456 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4459 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4496 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4499 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4543 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4546 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4573 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4576 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4604 src/dps8/dps8_eis.c if (TA1 == TA2) TA2 4606 src/dps8/dps8_eis.c if (e -> TA1 == e -> TA2) TA2 4764 src/dps8/dps8_eis.c switch (TA2) TA2 4766 src/dps8/dps8_eis.c switch (e -> TA2) TA2 4820 src/dps8/dps8_eis.c (TA2 == 2); // (6-4 move) TA2 4823 src/dps8/dps8_eis.c (e -> TA2 == 2); // (6-4 move) TA2 4838 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4841 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4869 src/dps8/dps8_eis.c TA2 == CTA9 && TA2 4872 src/dps8/dps8_eis.c e -> TA2 == CTA9 && TA2 4904 src/dps8/dps8_eis.c if (TA1 == TA2) TA2 4906 src/dps8/dps8_eis.c if (e -> TA1 == e -> TA2) TA2 7078 src/dps8/dps8_eis.c uint dstTA = TA2; TA2 7083 src/dps8/dps8_eis.c uint dstTA = e->TA2; TA2 7100 src/dps8/dps8_eis.c switch (TA2) TA2 7102 src/dps8/dps8_eis.c switch (e -> TA2) TA2 7193 src/dps8/dps8_eis.c if (TA1 == TA2) TA2 7195 src/dps8/dps8_eis.c if (e->TA1 == e->TA2)